Jarrod A. Roy

According to our database1, Jarrod A. Roy authored at least 26 papers between 2004 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
The ISPD-2011 routability-driven placement contest and benchmark suite.
Proceedings of the 2011 International Symposium on Physical Design, 2011

2010
Ending Piracy of Integrated Circuits.
IEEE Computer, 2010

ITOP: integrating timing optimization within placement.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Completing high-quality global routes.
Proceedings of the 2010 International Symposium on Physical Design, 2010

What makes a design difficult to route.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Design-hierarchy aware mixed-size placement for routability optimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
Solving modern mixed-size placement instances.
Integr., 2009

CRISP: Congestion reduction by iterated spreading during placement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Partitioning-Based Methods.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fine Control of Local Whitespace in Placement.
VLSI Design, 2008

Constraint-driven floorplan repair.
ACM Trans. Design Autom. Electr. Syst., 2008

High-Performance Routing at the Nanometer Scale.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Sidewinder: a scalable ILP-based router.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

The coming of age of (academic) global routing.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Circuit CAD Tools as a Security Threat.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

EPIC: Ending Piracy of Integrated Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

Protecting bus-based hardware IP by secret sharing.
Proceedings of the 45th Design Automation Conference, 2008

2007
ECO-System: Embracing the Change in Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
Min-cut floorplacement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Satisfying whitespace requirements in top-down placement.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Seeing the forest and the trees: Steiner wirelength optimization in placemen.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2005
Resolution cannot polynomially simulate compressed-BFS.
Ann. Math. Artif. Intell., 2005

Capo: robust and scalable open-source min-cut floorplacer.
Proceedings of the 2005 International Symposium on Physical Design, 2005

2004
Unification of partitioning, placement and floorplanning.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004


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