Rajeev Murgai

According to our database, Rajeev Murgai authored at least 46 papers between 1989 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

SAT-based redundancy removal.

Krishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2015

Technology-Dependent Logic Optimization.

Rajeev Murgai

Proc. IEEE, 2015

2009

Efficient Power Network Analysis Considering Multidomain Clock Gating.

Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.

Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng

Proceedings of the Design, Automation and Test in Europe, 2008

2007

An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.

Vineet Wason, Rajeev Murgai, William W. Walker

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Design and Analysis of "Tree+Local Meshes" Clock Architecture.

Gustavo R. Wilke, Rajeev Murgai

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Fast power network analysis with multiple clock domains.

Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Accurate Substrate Noise Analysis Based on Library Module Characterization.

Subodh M. Reddy, Rajeev Murgai

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Clock Distribution Architectures: A Comparative Study.

Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Analyzing timing uncertainty in mesh-based clock architectures.

Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction.

Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.

Rajeev Murgai

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A sliding window scheme for accurate clock mesh analysis.

Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

Macromodeling of digital libraries for substrate noise analysis.

Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.

Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction.

Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury

Proceedings of the 2004 Design, 2004

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.

Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori

Proceedings of the 2004 Design, 2004

2003

On the problem of gate assignment under different rise and fall delays.

Arlindo L. Oliveira, Rajeev Murgai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

PDL: A New Physical Synthesis Methodology.

Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

Layout-Driven Timing Optimization by Generalized De Morgan Transform.

Supratik Chakraborty, Rajeev Murgai

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Net Buffering in the Presence of Multiple Timing Views.

Rajeev Murgai

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001

Complexity Of Minimum-Delay Gate Resizing.

Supratik Chakraborty, Rajeev Murgai

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Efficient global fanout optimization algorithms.

Rajeev Murgai

Proceedings of ASP-DAC 2001, 2001

2000

Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization.

Rajeev Murgai

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays.

Arlindo L. Oliveira, Rajeev Murgai

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Layout-Driven Area-Constrained Timing Optimization by Net Buffering.

Rajeev Murgai

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Efficient Scheduling Techniques for ROBDD Construction.

Rajeev Murgai, Jawahar Jain, Masahiro Fujita

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Speeding Up Look-up-Table Driven Logic Simulation.

Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita

Proceedings of the VLSI: Systems on a Chip, 1999

On the global fanout optimization problem.

Rajeev Murgai

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Performance optimization under rise and fall parameters.

Rajeev Murgai

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

On Reducing Transitions Through Data Modifications.

Rajeev Murgai, Masahiro Fujita

Proceedings of the 1999 Design, 1999

1998

Using Complementation and Resequencing to Minimize Transitions.

Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira

Proceedings of the 35th Conference on Design Automation, 1998

1997

Some Recent Advances in Software and Hardware Logic Simulation.

Rajeev Murgai, Masahiro Fujita

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Speeding up technology-independent timing optimization by network partitioning.

Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1995

Logic synthesis for a single large look-up table.

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Decomposition of logic functions for minimum transition activity.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Optimum Functional Decomposition Using Encoding.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 31st Conference on Design Automation, 1994

1993

Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Cube-packing and two-level minimization.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Sequential Synthesis for Table Look Up Programmable Gate Arrays.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

An Improved Synthesis Algorithm for Multiplexor-Based PGA's.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 29th Design Automation Conference, 1992

1991

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.

Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Improved Logic Synthesis Algorithms for Table Look Up Architectures.

Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On Clustering for Minimum Delay/Area.

Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Logic Synthesis for Programmable Gate Arrays.

Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

SLIP: a software environment for system level interactive partitioning.

Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989