Rajeev Murgai

According to our database1, Rajeev Murgai authored at least 46 papers between 1989 and 2018.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
SAT-based redundancy removal.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2015
Technology-Dependent Logic Optimization.
Proc. IEEE, 2015

2009
Efficient Power Network Analysis Considering Multidomain Clock Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Design and Analysis of "Tree+Local Meshes" Clock Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Fast power network analysis with multiple clock domains.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Accurate Substrate Noise Analysis Based on Library Module Characterization.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Clock Distribution Architectures: A Comparative Study.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Analyzing timing uncertainty in mesh-based clock architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A sliding window scheme for accurate clock mesh analysis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Macromodeling of digital libraries for substrate noise analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction.
Proceedings of the 2004 Design, 2004

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.
Proceedings of the 2004 Design, 2004

2003
On the problem of gate assignment under different rise and fall delays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

PDL: A New Physical Synthesis Methodology.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Layout-Driven Timing Optimization by Generalized De Morgan Transform.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Net Buffering in the Presence of Multiple Timing Views.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001
Complexity Of Minimum-Delay Gate Resizing.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Efficient global fanout optimization algorithms.
Proceedings of ASP-DAC 2001, 2001

2000
Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Layout-Driven Area-Constrained Timing Optimization by Net Buffering.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Efficient Scheduling Techniques for ROBDD Construction.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Speeding Up Look-up-Table Driven Logic Simulation.
Proceedings of the VLSI: Systems on a Chip, 1999

On the global fanout optimization problem.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Performance optimization under rise and fall parameters.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

On Reducing Transitions Through Data Modifications.
Proceedings of the 1999 Design, 1999

1998
Using Complementation and Resequencing to Minimize Transitions.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Some Recent Advances in Software and Hardware Logic Simulation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Speeding up technology-independent timing optimization by network partitioning.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1995
Logic synthesis for a single large look-up table.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Decomposition of logic functions for minimum transition activity.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Optimum Functional Decomposition Using Encoding.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Cube-packing and two-level minimization.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Sequential Synthesis for Table Look Up Programmable Gate Arrays.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
An Improved Synthesis Algorithm for Multiplexor-Based PGA's.
Proceedings of the 29th Design Automation Conference, 1992

1991
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Improved Logic Synthesis Algorithms for Table Look Up Architectures.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On Clustering for Minimum Delay/Area.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Logic Synthesis for Programmable Gate Arrays.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
SLIP: a software environment for system level interactive partitioning.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


  Loading...