Igor L. Markov

Robert Wille

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Approximation of Quantum States Using Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

The N3XT Approach to Energy-Efficient Abundant-Data Computing.

[BibT_eX]

[DOI]

Proc. IEEE, 2019

2018

Quantum Supremacy Is Both Closer and Farther than It Appears.

[BibT_eX]

[DOI]

CoRR, 2018

Optimal die placement for interposer-based 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2016

Circuit Placement.

[BibT_eX]

[DOI]

Andrew A. Kennings

Encyclopedia of Algorithms, 2016

Impact of Future Technologies on Architecture.

[BibT_eX]

[DOI]

IEEE Micro, 2016

2015

Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking.

[BibT_eX]

[DOI]

Stephen M. Plaza

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Simulation of Quantum Circuits via Stabilizer Frames.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Progress and Challenges in VLSI Placement Research.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.

[BibT_eX]

[DOI]

Computer, 2015

2014

On the geometry of stabilizer states.

[BibT_eX]

[DOI]

Andrew W. Cross

Quantum Inf. Comput., 2014

Limits on fundamental limits to computation.

[BibT_eX]

[DOI]

Nat., 2014

A review of "Memcomputing NP-complete problems in polynomial time using polynomial resources" (arXiv: 1411.4798).

[BibT_eX]

[DOI]

CoRR, 2014

SuperPUF: integrating heterogeneous physically unclonable functions.

[BibT_eX]

[DOI]

Michael Wang

Andrew Yates

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Protecting integrated circuits from piracy with test-aware logic locking.

[BibT_eX]

[DOI]

Stephen M. Plaza

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 166, Springer, ISBN: 978-1-4614-1355-4, 2013

Design, Analysis and Test of Logic Circuits Under Uncertainty

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 115, Springer, ISBN: 978-90-481-9643-2, 2013

On bottleneck analysis in stochastic stream processing.

[BibT_eX]

[DOI]

Raj Rao Nadakuditi

ACM Trans. Design Autom. Electr. Syst., 2013

Synthesis and optimization of reversible circuits - a survey.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2013

Quantum Circuits for GCD Computation with $O(n \log n)$ Depth and O(n) Ancillae

[BibT_eX]

[DOI]

CoRR, 2013

Faster Quantum Number Factoring via Circuit Synthesis

[BibT_eX]

[DOI]

CoRR, 2013

SimPL: an algorithm for placing VLSI circuits.

[BibT_eX]

[DOI]

Commun. ACM, 2013

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

Quipu: High-performance simulation of quantum circuits using stabilizer frames.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Generalized Boolean symmetries through nested partition refinement.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

High-performance gate sizing with a signoff timer.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

ClockPUF: physical unclonable functions based on clock networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Taming the complexity of coordinated place and route.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

The nature of optimization problem challenges in physical synthesis.

[BibT_eX]

[DOI]

Ismail Bustany

Martin D. F. Wong

Proceedings of the American Control Conference, 2013

2012

Obstacle-Aware Clock-Tree Shaping During Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Assembling 2-D Blocks Into 3-D Chips.

[BibT_eX]

[DOI]

Johann Knechtel

Jens Lienig

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

SimPL: An Effective Placement Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Constant-optimized quantum circuits for modular multiplication and exponentiation.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2012

Efficient Inner-product Algorithm for Stabilizer States

[BibT_eX]

[DOI]

Andrew W. Cross

CoRR, 2012

Conflict Anticipation in the Search for Graph Automorphisms.

[BibT_eX]

[DOI]

Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2012

MAPLE: multilevel adaptive placement for mixed-size designs.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Charles J. Alpert

Shyam Ramji

Proceedings of the International Symposium on Physical Design, 2012

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Sensitivity-guided metaheuristics for accurate discrete gate sizing.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

RTL analysis and modifications for improving at-speed test.

[BibT_eX]

[DOI]

Hong-Zu Chou

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Graph Symmetry Detection and Canonical Labeling: Differences and Synergies.

[BibT_eX]

[DOI]

Proceedings of the Turing-100, 2012

Securely Sealing Multi-FPGA Systems.

[BibT_eX]

[DOI]

Tim Güneysu

André Weimerskirch

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

CONTANGO: Integrated Optimization of SoC Clock Networks.

[BibT_eX]

[DOI]

VLSI Design, 2011

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Gi-Joon Nam

IEEE Micro, 2011

Getting Your Bits in Order.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)].

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

Constant-Degree Graph Expansions that Preserve Treewidth.

[BibT_eX]

[DOI]

Yaoyun Shi

Algorithmica, 2011

Assembling 2D blocks into 3D chips.

[BibT_eX]

[DOI]

Johann Knechtel

Jens Lienig

Proceedings of the 2011 International Symposium on Physical Design, 2011

Algorithmic tuning of clock trees and derived non-tree structures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multilevel tree fusion for robust clock networks.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A SimPLR method for routability-driven placement.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

VLSI Physical Design - From Graph Partitioning to Timing Closure.

[BibT_eX]

[DOI]

Springer, ISBN: 978-90-481-9590-9, 2011

2010

Logic synthesis and circuit customization using extensive external don't-cares.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Fast equivalence - checking for quantum circuits.

[BibT_eX]

[DOI]

Shigeru Yamashita

Quantum Inf. Comput., 2010

Speeding Up Physical Synthesis with Transactional Timing Analysis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2010

Chips in 3D.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2010

Master numerical tasks with ease.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2010

Ending Piracy of Integrated Circuits.

[BibT_eX]

[DOI]

Computer, 2010

Symmetry and Satisfiability: An Update.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2010

Completing high-quality global routes.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

SPIRE: A retiming-based physical-synthesis transformation system.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Low-power clock trees for CPUs.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Large-scale Boolean matching.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Spinto: High-performance energy minimization in spin glasses.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

On the costs and benefits of stochasticity in stream processing.

[BibT_eX]

[DOI]

Raj R. Nadakuditi

Proceedings of the 47th Design Automation Conference, 2010

2009

Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 32, Springer, ISBN: 978-1-4020-9364-7, 2009

Signature-Based SER Analysis and Design of Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

On the CNOT-cost of TOFFOLI gates.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2009

Solving modern mixed-size placement instances.

[BibT_eX]

[DOI]

Integr., 2009

Book Review: A physical-design picture book.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Incremental Verification with Error Detection, Diagnosis, and Visualization.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

High-performance Energy Minimization with Applications to Adiabatic Quantum Computing.

[BibT_eX]

[DOI]

CoRR, 2009

Dynamic symmetry-breaking for Boolean satisfiability.

[BibT_eX]

[DOI]

Ann. Math. Artif. Intell., 2009

CRISP: Congestion reduction by iterated spreading during placement.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Gi-Joon Nam

Charles J. Alpert

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Customizing IP cores for system-on-chip designs using extensive external don't-cares.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Improving testability and soft-error resilience through retiming.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Quantum Circuit Simulation.

[BibT_eX]

[DOI]

Springer, ISBN: 978-90-481-3064-1, 2009

2008

Partitioning-Based Methods.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Circuit Placement.

[BibT_eX]

[DOI]

Andrew A. Kennings

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Fine Control of Local Whitespace in Placement.

[BibT_eX]

[DOI]

VLSI Design, 2008

Constraint-driven floorplan repair.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

High-Performance Routing at the Nanometer Scale.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.

[BibT_eX]

[DOI]

Stephen Plaza

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fixing Design Errors With Counterexamples and Resynthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Simulating Quantum Computation by Contracting Tensor Networks.

[BibT_eX]

[DOI]

Yaoyun Shi

SIAM J. Comput., 2008

Optimal synthesis of linear reversible circuits.

[BibT_eX]

[DOI]

Ketan N. Patel

Quantum Inf. Comput., 2008

SafeResynth: A new technique for physical synthesis.

[BibT_eX]

[DOI]

Integr., 2008

Automating Postsilicon Debugging and Repair.

[BibT_eX]

[DOI]

Computer, 2008

Sidewinder: a scalable ILP-based router.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Optimizing non-monotonic interconnect using functional simulation and logic restructuring.

[BibT_eX]

[DOI]

Stephen Plaza

Proceedings of the 2008 International Symposium on Physical Design, 2008

The coming of age of (academic) global routing.

[BibT_eX]

[DOI]

Michael D. Moffitt

Proceedings of the 2008 International Symposium on Physical Design, 2008

Reap what you sow: spare cells for post-silicon metal fix.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

On the decreasing significance of large standard cells in technology mapping.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Circuit CAD Tools as a Security Threat.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

EPIC: Ending Piracy of Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Random Stimulus Generation using Entropy and XOR Constraints.

[BibT_eX]

[DOI]

Stephen Plaza

Proceedings of the Design, Automation and Test in Europe, 2008

Protecting bus-based hardware IP by secret sharing.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

On the role of timing masking in reliable logic circuit design.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Faster symmetry discovery using sparsity of symmetries.

[BibT_eX]

[DOI]

Paul T. Darga

Proceedings of the 45th Design Automation Conference, 2008

2007

Hypergraph Partitioning and Clustering.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

Postplacement rewiring by exhaustive search for functional symmetries.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

ECO-System: Embracing the Change in Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Simulation-Based Bug Trace Minimization With BMC-Based Refinement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Solution and Optimization of Systems of Pseudo-Boolean Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Symmetry breaking for pseudo-Boolean formulas.

[BibT_eX]

[DOI]

ACM J. Exp. Algorithmics, 2007

Special issue on System-Level Interconnect Prediction.

[BibT_eX]

[DOI]

Louis Scheffer

Dirk Stroobandt

Integr., 2007

Tracking Uncertainty with Probabilistic Logic Circuit Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Checking equivalence of quantum circuits and states.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Enhancing design robustness with reliability-aware resynthesis and logic simulation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automating post-silicon debugging and repair.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automatic error diagnosis and correction for RTL designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Node Mergers in the Presence of Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Safe Delay Optimization for Physical Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

Synthesis of quantum-logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Min-cut floorplacement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Efficient Symmetry Breaking for Boolean Satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Data structures and algorithms for simplifying reversible circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2006

Breaking Instance-Independent Symmetries In Exact Graph Coloring.

[BibT_eX]

[DOI]

J. Artif. Intell. Res., 2006

On whitespace and stability in physical synthesis.

[BibT_eX]

[DOI]

Paul G. Villarrubia

Integr., 2006

A Layered Software Architecture for Quantum Computing Design Tools.

[BibT_eX]

[DOI]

Computer, 2006

Satisfying whitespace requirements in top-down placement.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Seeing the forest and the trees: Steiner wirelength optimization in placemen.

[BibT_eX]

[DOI]

James F. Lu

Proceedings of the 2006 International Symposium on Physical Design, 2006

Solving hard instances of floorplacement.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

On-Chip Test Generation Using Linear Subspaces.

[BibT_eX]

[DOI]

Ramashis Das

Proceedings of the 11th European Test Symposium, 2006

Constraint-driven floorplan repair.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Utility of the OpenAccess database in academic research.

[BibT_eX]

[DOI]

Philip Chong

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Combinatorial techniques for mixed-size placement.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Graph-based simulation of quantum computation in the density matrix representation.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2005

Quantum circuits for incompletely specified two-qubit operators.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2005

Is quantum search practical?

[BibT_eX]

[DOI]

Comput. Sci. Eng., 2005

Resolution cannot polynomially simulate compressed-BFS.

[BibT_eX]

[DOI]

DoRon B. Motter

Ann. Math. Artif. Intell., 2005

Toward Quality EDA Tools and Tool Flows Through High-Performance Computing.

[BibT_eX]

[DOI]

Aaron N. Ng

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Early research experience with OpenAccess gear: an open source development environment for physical design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Capo: robust and scalable open-source min-cut floorplacer.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Are floorplan representations important in digital design?

[BibT_eX]

[DOI]

Hayward H. Chan

Proceedings of the 2005 International Symposium on Physical Design, 2005

Post-placement rewiring and rebuffering by exhaustive search for functional symmetries.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Logic circuit testing for transient faults.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Uniformly-Switching Logic for Cryptographic Hardware.

[BibT_eX]

[DOI]

Dmitri Maslov

Proceedings of the 2005 Design, 2005

Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Dynamic symmetry-breaking for improved Boolean optimization.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Error-correction and crosstalk avoidance in DSM busses.

[BibT_eX]

[DOI]

Ketan N. Patel

IEEE Trans. Very Large Scale Integr. Syst., 2004

Fault testing for reversible circuits.

[BibT_eX]

[DOI]

Ketan N. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Benchmarking for large-scale placement and beyond.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Asymptotically optimal circuits for arbitrary n-qubit diagonal comutations.

[BibT_eX]

[DOI]

Quantum Inf. Comput., 2004

MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2004

Unification of partitioning, placement and floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Constructive benchmarking for placement.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

On legalization of row-based placements.

[BibT_eX]

[DOI]

Sherief Reda

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Practical slicing and non-slicing block-packing without simulated annealing.

[BibT_eX]

[DOI]

Hayward H. Chan

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

High-Performance QuIDD-Based Simulation of Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Smaller Two-Qubit Circuits for Quantum Communication and Computation.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Boosting: Min-Cut Placement with Improved Signal Delay.

[BibT_eX]

[DOI]

Sherief Reda

Proceedings of the 2004 Design, 2004

AMUSE: a minimally-unsatisfiable subformula extractor.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Exploiting structure in symmetry detection for CNF.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Automatically Exploiting Symmetries in Constraint Programming.

[BibT_eX]

[DOI]

Arathi Ramani

Proceedings of the Recent Advances in Constraints, 2004

ShatterPB: symmetry-breaking for pseudo-Boolean formulas.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Improved a priori interconnect predictions and technology extrapolation in the GTX system.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Fixed-outline floorplanning: enabling hierarchical design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Synthesis of reversible logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Hierarchical whitespace allocation in top-down placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Solving difficult instances of Boolean satisfiability in the presence of symmetry.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Improving Gate-Level Simulation of Quantum Circuits.

[BibT_eX]

[DOI]

Quantum Inf. Process., 2003

Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Combining Two Local Search Approaches to Hypergraph Partitioning.

[BibT_eX]

[DOI]

Arathi Ramani

Proceedings of the IJCAI-03, 2003

On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.

[BibT_eX]

[DOI]

Paul Villarrubia

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

FORCE: a fast and easy-to-implement variable-ordering heuristic.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

An arbitrary twoqubit computation In 23 elementary gates or less.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Shatter: efficient symmetry-breaking for boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Gate-level simulation of quantum circuits.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Overcoming Resolution-Based Lower Bounds for SAT Solvers.

[BibT_eX]

DoRon B. Motter

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Efficient Gate and Input Ordering for Circuit-to-BDD Conversion.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Min-max placement for large-scale timing optimization.

[BibT_eX]

[DOI]

Stefanus Mantik

Proceedings of 2002 International Symposium on Physical Design, 2002

Consistent placement of macro-blocks using floorplanning and standard-cell placement.

[BibT_eX]

[DOI]

Proceedings of 2002 International Symposium on Physical Design, 2002

Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Reversible logic circuit synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Generic ILP versus specialized 0-1 ILP: an update.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Solving difficult SAT instances in the presence of symmetry.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

A Compressed Breadth-First Search for Satisfiability.

[BibT_eX]

[DOI]

DoRon B. Motter

Proceedings of the Algorithm Engineering and Experiments, 4th International Workshop, 2002

2001

Constraint-based watermarking techniques for design IP protection.

[BibT_eX]

[DOI]

William H. Mangione-Smith

John C. Lach

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Fixed-outline Floorplanning through Better Local Search.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Faster SAT and Smaller BDDs via Common Function Structure.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Iterative Partitioning with Varying Node Weights.

[BibT_eX]

[DOI]

VLSI Design, 2000

Optimal partitioners and end-case placers for standard-cell layout.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Hypergraph partitioning with fixed vertices [VLSI CAD].

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning.

[BibT_eX]

[DOI]

ACM J. Exp. Algorithmics, 2000

Web-based frameworks to enable CAD RD (abstract).

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Can recursive bisection alone produce routable placements?

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

GTX: the MARCO GSRC technology extrapolation system.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Analytical minimization of half-perimeter wirelength.

[BibT_eX]

[DOI]

Andrew A. Kennings

Proceedings of ASP-DAC 2000, 2000

Improved algorithms for hypergraph bipartitioning.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.

[BibT_eX]

[DOI]

VLSI Design, 1999

On wirelength estimations for row-based placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Partitioning with terminals: a "new" problem and new benchmarks.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

Hypergraph Partitioning with Fixed Vertices.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Function Smoothing with Applications to VLSI Layout.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Algorithm Engineering and Experimentation, 1999

1998

Faster minimization of linear wirelength for global placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Robust IP Watermarking Methodologies for Physical Design.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Watermarking Techniques for Intellectual Property Protection.

[BibT_eX]

[DOI]