Igor L. Markov

According to our database1, Igor L. Markov authored at least 211 papers between 1997 and 2020.

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Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to optimization methods in electronic design automation".

Timeline

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Bibliography

2020
Faster Schrödinger-style simulation of quantum circuits.
CoRR, 2020

Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond.
CoRR, 2020

Approximation of Quantum States Using Decision Diagrams.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
The N3XT Approach to Energy-Efficient Abundant-Data Computing.
Proceedings of the IEEE, 2019

2018
Quantum Supremacy Is Both Closer and Farther than It Appears.
CoRR, 2018

Optimal die placement for interposer-based 3D ICs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2016
Circuit Placement.
Encyclopedia of Algorithms, 2016

Impact of Future Technologies on Architecture.
IEEE Micro, 2016

2015
Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Simulation of Quantum Circuits via Stabilizer Frames.
IEEE Trans. Computers, 2015

Progress and Challenges in VLSI Placement Research.
Proceedings of the IEEE, 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
Computer, 2015

2014
On the geometry of stabilizer states.
Quantum Inf. Comput., 2014

Limits on fundamental limits to computation.
Nat., 2014

A review of "Memcomputing NP-complete problems in polynomial time using polynomial resources" (arXiv: 1411.4798).
CoRR, 2014

SuperPUF: integrating heterogeneous physically unclonable functions.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Protecting integrated circuits from piracy with test-aware logic locking.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Multi-Objective Optimization in Physical Synthesis of Integrated Circuits
Lecture Notes in Electrical Engineering 166, Springer, ISBN: 978-1-4614-1355-4, 2013

Design, Analysis and Test of Logic Circuits Under Uncertainty
Lecture Notes in Electrical Engineering 115, Springer, ISBN: 978-90-481-9643-2, 2013

On bottleneck analysis in stochastic stream processing.
ACM Trans. Design Autom. Electr. Syst., 2013

Synthesis and optimization of reversible circuits - a survey.
ACM Comput. Surv., 2013

Quantum Circuits for GCD Computation with $O(n \log n)$ Depth and O(n) Ancillae
CoRR, 2013

Faster Quantum Number Factoring via Circuit Synthesis
CoRR, 2013

SimPL: an algorithm for placing VLSI circuits.
Commun. ACM, 2013

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms.
Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

Quipu: High-performance simulation of quantum circuits using stabilizer frames.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Generalized Boolean symmetries through nested partition refinement.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

High-performance gate sizing with a signoff timer.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

ClockPUF: physical unclonable functions based on clock networks.
Proceedings of the Design, Automation and Test in Europe, 2013

Taming the complexity of coordinated place and route.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

The nature of optimization problem challenges in physical synthesis.
Proceedings of the American Control Conference, 2013

2012
Obstacle-Aware Clock-Tree Shaping During Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Assembling 2-D Blocks Into 3-D Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

SimPL: An Effective Placement Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Constant-optimized quantum circuits for modular multiplication and exponentiation.
Quantum Inf. Comput., 2012

Efficient Inner-product Algorithm for Stabilizer States
CoRR, 2012

Conflict Anticipation in the Search for Graph Automorphisms.
Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2012

MAPLE: multilevel adaptive placement for mixed-size designs.
Proceedings of the International Symposium on Physical Design, 2012

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Sensitivity-guided metaheuristics for accurate discrete gate sizing.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

RTL analysis and modifications for improving at-speed test.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Graph Symmetry Detection and Canonical Labeling: Differences and Synergies.
Proceedings of the Turing-100, 2012

Securely Sealing Multi-FPGA Systems.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
CONTANGO: Integrated Optimization of SoC Clock Networks.
VLSI Design, 2011

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.
IEEE Micro, 2011

Getting Your Bits in Order.
IEEE Des. Test Comput., 2011

EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)].
IEEE Des. Test Comput., 2011

Constant-Degree Graph Expansions that Preserve Treewidth.
Algorithmica, 2011

Assembling 2D blocks into 3D chips.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Algorithmic tuning of clock trees and derived non-tree structures.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multilevel tree fusion for robust clock networks.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A SimPLR method for routability-driven placement.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

VLSI Physical Design - From Graph Partitioning to Timing Closure.
Springer, ISBN: 978-90-481-9590-9, 2011

2010
Logic synthesis and circuit customization using extensive external don't-cares.
ACM Trans. Design Autom. Electr. Syst., 2010

Fast equivalence - checking for quantum circuits.
Quantum Inf. Comput., 2010

Speeding Up Physical Synthesis with Transactional Timing Analysis.
IEEE Des. Test Comput., 2010

Chips in 3D.
IEEE Des. Test Comput., 2010

Master numerical tasks with ease.
IEEE Des. Test Comput., 2010

Ending Piracy of Integrated Circuits.
Computer, 2010

Symmetry and Satisfiability: An Update.
Proceedings of the Theory and Applications of Satisfiability Testing, 2010

Completing high-quality global routes.
Proceedings of the 2010 International Symposium on Physical Design, 2010

SPIRE: A retiming-based physical-synthesis transformation system.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Low-power clock trees for CPUs.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Large-scale Boolean matching.
Proceedings of the Design, Automation and Test in Europe, 2010

Spinto: High-performance energy minimization in spin glasses.
Proceedings of the Design, Automation and Test in Europe, 2010

On the costs and benefits of stochasticity in stream processing.
Proceedings of the 47th Design Automation Conference, 2010

2009
Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair
Lecture Notes in Electrical Engineering 32, Springer, ISBN: 978-1-4020-9364-7, 2009

Signature-Based SER Analysis and Design of Logic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

On the CNOT-cost of TOFFOLI gates.
Quantum Inf. Comput., 2009

Solving modern mixed-size placement instances.
Integr., 2009

Book Review: A physical-design picture book.
IEEE Des. Test Comput., 2009

Incremental Verification with Error Detection, Diagnosis, and Visualization.
IEEE Des. Test Comput., 2009

High-performance Energy Minimization with Applications to Adiabatic Quantum Computing.
CoRR, 2009

Dynamic symmetry-breaking for Boolean satisfiability.
Ann. Math. Artif. Intell., 2009

CRISP: Congestion reduction by iterated spreading during placement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Customizing IP cores for system-on-chip designs using extensive external don't-cares.
Proceedings of the Design, Automation and Test in Europe, 2009

Improving testability and soft-error resilience through retiming.
Proceedings of the 46th Design Automation Conference, 2009

Quantum Circuit Simulation.
Springer, ISBN: 978-90-481-3064-1, 2009

2008
Partitioning-Based Methods.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Circuit Placement.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Fine Control of Local Whitespace in Placement.
VLSI Design, 2008

Constraint-driven floorplan repair.
ACM Trans. Design Autom. Electr. Syst., 2008

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.
ACM Trans. Design Autom. Electr. Syst., 2008

High-Performance Routing at the Nanometer Scale.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Fixing Design Errors With Counterexamples and Resynthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Simulating Quantum Computation by Contracting Tensor Networks.
SIAM J. Comput., 2008

Optimal synthesis of linear reversible circuits.
Quantum Inf. Comput., 2008

SafeResynth: A new technique for physical synthesis.
Integr., 2008

Automating Postsilicon Debugging and Repair.
Computer, 2008

Sidewinder: a scalable ILP-based router.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Optimizing non-monotonic interconnect using functional simulation and logic restructuring.
Proceedings of the 2008 International Symposium on Physical Design, 2008

The coming of age of (academic) global routing.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Reap what you sow: spare cells for post-silicon metal fix.
Proceedings of the 2008 International Symposium on Physical Design, 2008

On the decreasing significance of large standard cells in technology mapping.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Circuit CAD Tools as a Security Threat.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

EPIC: Ending Piracy of Integrated Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

Random Stimulus Generation using Entropy and XOR Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Protecting bus-based hardware IP by secret sharing.
Proceedings of the 45th Design Automation Conference, 2008

On the role of timing masking in reliable logic circuit design.
Proceedings of the 45th Design Automation Conference, 2008

Faster symmetry discovery using sparsity of symmetries.
Proceedings of the 45th Design Automation Conference, 2008

2007
Hypergraph Partitioning and Clustering.
Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

Postplacement rewiring by exhaustive search for functional symmetries.
ACM Trans. Design Autom. Electr. Syst., 2007

ECO-System: Embracing the Change in Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Simulation-Based Bug Trace Minimization With BMC-Based Refinement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Solution and Optimization of Systems of Pseudo-Boolean Constraints.
IEEE Trans. Computers, 2007

Symmetry breaking for pseudo-Boolean formulas.
ACM J. Exp. Algorithmics, 2007

Special issue on System-Level Interconnect Prediction.
Integr., 2007

Tracking Uncertainty with Probabilistic Logic Circuit Testing.
IEEE Des. Test Comput., 2007

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Checking equivalence of quantum circuits and states.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Enhancing design robustness with reliability-aware resynthesis and logic simulation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automating post-silicon debugging and repair.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Automatic error diagnosis and correction for RTL designs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Node Mergers in the Presence of Don't Cares.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Safe Delay Optimization for Physical Synthesis.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
Synthesis of quantum-logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Min-cut floorplacement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Efficient Symmetry Breaking for Boolean Satisfiability.
IEEE Trans. Computers, 2006

Data structures and algorithms for simplifying reversible circuits.
ACM J. Emerg. Technol. Comput. Syst., 2006

Breaking Instance-Independent Symmetries In Exact Graph Coloring.
J. Artif. Intell. Res., 2006

On whitespace and stability in physical synthesis.
Integr., 2006

A Layered Software Architecture for Quantum Computing Design Tools.
Computer, 2006

Satisfying whitespace requirements in top-down placement.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Seeing the forest and the trees: Steiner wirelength optimization in placemen.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Solving hard instances of floorplacement.
Proceedings of the 2006 International Symposium on Physical Design, 2006

On-Chip Test Generation Using Linear Subspaces.
Proceedings of the 11th European Test Symposium, 2006

Constraint-driven floorplan repair.
Proceedings of the 43rd Design Automation Conference, 2006

Utility of the OpenAccess database in academic research.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Combinatorial techniques for mixed-size placement.
ACM Trans. Design Autom. Electr. Syst., 2005

Graph-based simulation of quantum computation in the density matrix representation.
Quantum Inf. Comput., 2005

Quantum circuits for incompletely specified two-qubit operators.
Quantum Inf. Comput., 2005

Is quantum search practical?
Comput. Sci. Eng., 2005

Resolution cannot polynomially simulate compressed-BFS.
Ann. Math. Artif. Intell., 2005

Toward Quality EDA Tools and Tool Flows Through High-Performance Computing.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Early research experience with OpenAccess gear: an open source development environment for physical design.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Capo: robust and scalable open-source min-cut floorplacer.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Are floorplan representations important in digital design?
Proceedings of the 2005 International Symposium on Physical Design, 2005

Post-placement rewiring and rebuffering by exhaustive search for functional symmetries.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Logic circuit testing for transient faults.
Proceedings of the 10th European Test Symposium, 2005

Uniformly-Switching Logic for Cryptographic Hardware.
Proceedings of the 2005 Design, 2005

Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices.
Proceedings of the 2005 Design, 2005

Dynamic symmetry-breaking for improved Boolean optimization.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Error-correction and crosstalk avoidance in DSM busses.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Fault testing for reversible circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Benchmarking for large-scale placement and beyond.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Asymptotically optimal circuits for arbitrary n-qubit diagonal comutations.
Quantum Inf. Comput., 2004

MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation.
J. UCS, 2004

Unification of partitioning, placement and floorplanning.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Constructive benchmarking for placement.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

On legalization of row-based placements.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Practical slicing and non-slicing block-packing without simulated annealing.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

High-Performance QuIDD-Based Simulation of Quantum Circuits.
Proceedings of the 2004 Design, 2004

Smaller Two-Qubit Circuits for Quantum Communication and Computation.
Proceedings of the 2004 Design, 2004

Boosting: Min-Cut Placement with Improved Signal Delay.
Proceedings of the 2004 Design, 2004

AMUSE: a minimally-unsatisfiable subformula extractor.
Proceedings of the 41th Design Automation Conference, 2004

Exploiting structure in symmetry detection for CNF.
Proceedings of the 41th Design Automation Conference, 2004

Automatically Exploiting Symmetries in Constraint Programming.
Proceedings of the Recent Advances in Constraints, 2004

ShatterPB: symmetry-breaking for pseudo-Boolean formulas.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Improved a priori interconnect predictions and technology extrapolation in the GTX system.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Fixed-outline floorplanning: enabling hierarchical design.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Synthesis of reversible logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Hierarchical whitespace allocation in top-down placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Solving difficult instances of Boolean satisfiability in the presence of symmetry.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Improving Gate-Level Simulation of Quantum Circuits.
Quantum Inf. Process., 2003

Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Combining Two Local Search Approaches to Hypergraph Partitioning.
Proceedings of the IJCAI-03, 2003

On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

FORCE: a fast and easy-to-implement variable-ordering heuristic.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

An arbitrary twoqubit computation In 23 elementary gates or less.
Proceedings of the 40th Design Automation Conference, 2003

Shatter: efficient symmetry-breaking for boolean satisfiability.
Proceedings of the 40th Design Automation Conference, 2003

Gate-level simulation of quantum circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms.
IEEE Des. Test Comput., 2002

Overcoming Resolution-Based Lower Bounds for SAT Solvers.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Efficient Gate and Input Ordering for Circuit-to-BDD Conversion.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Min-max placement for large-scale timing optimization.
Proceedings of 2002 International Symposium on Physical Design, 2002

Consistent placement of macro-blocks using floorplanning and standard-cell placement.
Proceedings of 2002 International Symposium on Physical Design, 2002

Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Reversible logic circuit synthesis.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Generic ILP versus specialized 0-1 ILP: an update.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Solving difficult SAT instances in the presence of symmetry.
Proceedings of the 39th Design Automation Conference, 2002

A Compressed Breadth-First Search for Satisfiability.
Proceedings of the Algorithm Engineering and Experiments, 4th International Workshop, 2002

2001
Constraint-based watermarking techniques for design IP protection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Fixed-outline Floorplanning through Better Local Search.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Faster SAT and Smaller BDDs via Common Function Structure.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
Iterative Partitioning with Varying Node Weights.
VLSI Design, 2000

Optimal partitioners and end-case placers for standard-cell layout.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Hypergraph partitioning with fixed vertices [VLSI CAD].
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning.
ACM J. Exp. Algorithmics, 2000

Web-based frameworks to enable CAD RD (abstract).
Proceedings of the 37th Conference on Design Automation, 2000

Can recursive bisection alone produce routable placements?
Proceedings of the 37th Conference on Design Automation, 2000

GTX: the MARCO GSRC technology extrapolation system.
Proceedings of the 37th Conference on Design Automation, 2000

Analytical minimization of half-perimeter wirelength.
Proceedings of ASP-DAC 2000, 2000

Improved algorithms for hypergraph bipartitioning.
Proceedings of ASP-DAC 2000, 2000

1999
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.
VLSI Design, 1999

On wirelength estimations for row-based placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Partitioning with terminals: a "new" problem and new benchmarks.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Hypergraph Partitioning with Fixed Vertices.
Proceedings of the 36th Conference on Design Automation, 1999

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.
Proceedings of the 36th Conference on Design Automation, 1999

Function Smoothing with Applications to VLSI Layout.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning.
Proceedings of the Algorithm Engineering and Experimentation, 1999

1998
Faster minimization of linear wirelength for global placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Robust IP Watermarking Methodologies for Physical Design.
Proceedings of the 35th Conference on Design Automation, 1998

Watermarking Techniques for Intellectual Property Protection.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Faster minimization of linear wirelength for global placement.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Quadratic Placement Revisited.
Proceedings of the 34st Conference on Design Automation, 1997


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