Rajat Chauhan

According to our database1, Rajat Chauhan authored at least 13 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2019
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting.
IEEE J. Solid State Circuits, 2019

A K-Means-Galactic Swarm Optimization-Based Clustering Algorithm with Otsu's Entropy for Brain Tumor Detection.
Appl. Artif. Intell., 2019

2018
Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Gold Nanoparticles Conjugate Cancer-Targeting Aptamer and Gadolinium Chelate for MR Cancer Imaging.
Proceedings of the 2018 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2018

Engineering sequence and stimuli dependent doxorubicin release from anti-nucleolin aptamer coated gold nanoparticles.
Proceedings of the 2018 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2018

Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2015
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2013
Input Referred Offset Reduction in Very High Speed Differential Receivers.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2008
A Robust Level-Shifter Design for Adaptive Voltage Scaling.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2005
A high performance, high voltage output buffer in a low voltage CMOS process.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


  Loading...