Karthik Rajagopal

According to our database, Karthik Rajagopal authored at least 9 papers between 1998 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process.

Karthik Rajagopal

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Designing better strategies against human adversaries in network security games.

Rong Yang, Fei Fang, Albert Xin Jiang, Karthik Rajagopal, Milind Tambe, Rajiv T. Maheswaran

Proceedings of the International Conference on Autonomous Agents and Multiagent Systems, 2012

2009

An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process.

Karthik Rajagopal, Aatmesh, Vinod Menezes

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2005

How accurately can we model timing in a placement engine?

Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin

Proceedings of the 42nd Design Automation Conference, 2005

A high performance, high voltage output buffer in a low voltage CMOS process.

Rajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

Timing driven force directed placement with physical net constraints.

Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin

Proceedings of the 2003 International Symposium on Physical Design, 2003

Force directed mongrel with physical net constraints.

Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin

Proceedings of the 40th Design Automation Conference, 2003

2000

TACO: timing analysis with coupling.

Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi

Proceedings of the 37th Conference on Design Automation, 2000

1998

Determination of worst-case aggressor alignment for delay calculation.

Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998