Ramin Zanbaghi

According to our database, Ramin Zanbaghi authored at least 13 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique.

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez

IEEE J. Solid State Circuits, 2020

2019

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA.

Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC.

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique.

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer.

Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2013

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW.

Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez

IEEE J. Solid State Circuits, 2013

2012

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power.

Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW.

Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A new zero-optimization scheme for noise-coupled ΔΣ ADCs.

Ramin Zanbaghi, Terri S. Fiez, Gabor C. Temes

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A Novel Low Power Hybrid Loop Filter for Continuous-time Sigma-delta Modulators.

Ramin Zanbaghi, Terri S. Fiez

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

A Power Optimized Base-Band Circuitry for the Low-IF Receivers.

Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications.

Mohsen Moezzi, Ramin Zanbaghi, Mojtaba Atarodi, Armin Tajalli

Proceedings of the 13th IEEE International Conference on Electronics, 2006