Pedram Payandehnia

According to our database1, Pedram Payandehnia authored at least 16 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique.
IEEE J. Solid State Circuits, 2020

Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An Amplifier-Free 0-2 SAR-VCO MASH ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
A passive CMOS low-pass filter for high speed and high SNDR applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Multi-step counting ADC.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2012
A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE.
Microelectron. J., 2012

2011
A 12.5Gb/s active-inductor based transmitter for I/O applications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011


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