Kartikeya Mayaram

According to our database1, Kartikeya Mayaram authored at least 109 papers between 1986 and 2020.

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Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to coupled device and circuit simulation.".

Timeline

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Bibliography

2020
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique.
IEEE J. Solid State Circuits, 2020

2019
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4<sup>th</sup> order CT-ΔΣ modulator with 2<sup>nd</sup> order noise-shaping and pipelined SAR-VCO based quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation.
IEEE J. Solid State Circuits, 2018

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Fast start-up analysis of resonator based oscillators using a power generation method.
IET Circuits Devices Syst., 2016

JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications.
Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016

2015
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS.
IEEE J. Solid State Circuits, 2015

2014
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2014

A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2013

2012
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Design-Oriented Analysis of Circuits With Equality Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A Multiple-Input Boost Converter for Low-Power Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS.
IEEE J. Solid State Circuits, 2011

A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency.
IEEE J. Solid State Circuits, 2011

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
An Ultralow-Power Receiver for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2010

A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Digital PLL With a Stochastic Time-to-Digital Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Automated Design and Optimization of Low-Noise Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers.
IEEE J. Solid State Circuits, 2009

Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Sensitivity Analysis for Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks.
IEEE J. Solid State Circuits, 2008

Parameter variation analysis for voltage controlled oscillators in phase-locked loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Periodic Steady-State Analysis Augmented with Design Equality Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Noise tolerant oscillator design using perturbation projection vector analysis.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.
IEEE J. Solid State Circuits, 2007

Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Noise Simulation and Modeling for MEMS Varactor Based RF VCOs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Very Low Noise 4.2GHz Clapp VCOs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power BFSK Super-Regenerative Transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency.
Proceedings of the 44th Design Automation Conference, 2007

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Digitally-Enhanced Phase-Locking Circuits.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

CEDA Currents.
IEEE Des. Test Comput., 2006

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Dependence of LC VCO oscillation frequency on bias current.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip.
IEEE Trans. Very Large Scale Integr. Syst., 2005

On the numerical stability of Green's function for substrate coupling in integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

An efficient and robust method for ring-oscillator simulation using the harmonic-balance method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of supply and ground noise sensitivity in ring and LC oscillators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low spur fractional-N frequency synthesizer architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A green function-based parasitic extraction method for inhomogeneous substrate layers.
Proceedings of the 42nd Design Automation Conference, 2005

A multiple-probe approach for robust frequency domain ring oscillator simulation.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A new approach for ring oscillator simulation using the harmonic balance method.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Analysis of charge-pump phase-locked loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Silencer!: a tool for substrate noise coupling analysis.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An improved Z-parameter macro model for substrate noise coupling.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A physical and analytical model for substrate noise coupling analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A predictive methodology for accurate substrate parasitic extraction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An accurate and efficient estimation of switching noise in synchronous digital circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Accurate simulation of phase noise in RF MEMS VCOs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Frequency domain simulation of high-Q oscillators with homotopy methods.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Coupled Simulation of Circuit and Piezoelectric Laminates.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Symbolic Analysis of Nonlinear Analog Circuits.
Proceedings of the 2003 Design, 2003

2002
Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An efficient modeling approach for substrate noise coupling analysis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits].
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of CMOS RF LNAs with ESD protection.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of jitter in ring oscillators due to deterministic noise.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
A simple and accurate method for calculating the low frequency common-mode gain in a MOS differential amplifier with a current-mirror load.
IEEE Trans. Educ., 2000

Neural Network Design for Behavioral Model Generation with Shape Preserving Properties.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1999
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A scalable substrate noise coupling model for mixed-signal ICs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Comments on "A small-signal MOSFET model for radio frequency IC applications".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1993
Algorithms for transient three-dimensional mixed-level circuit and device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A new matrix solution technique for general circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
Coupling algorithms for mixed-level circuit and device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Analog integrated circuits for communication - principles, simulation and design.
Kluwer, ISBN: 978-0-7923-9089-3, 1990

1989
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Techniques for multilayer channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

CODECS: a fixed mixed-level device and circuit simulator.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986
Chameleon: a new multi-layer channel router.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986


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