Ramtilak Vemu

According to our database1, Ramtilak Vemu authored at least 8 papers between 2006 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
CEDA: Control-Flow Error Detection Using Assertions.
IEEE Trans. Computers, 2011

2009
Functionally valid gate-level peak power estimation for processors.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Budget-Dependent Control-Flow Error Detection.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

On efficient generation of instruction sequences to test for delay defects in a processor.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A low-cost concurrent error detection technique for processor control logic.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
ACCE: Automatic correction of control-flow errors.
Proceedings of the 2007 IEEE International Test Conference, 2007

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.
Proceedings of the 12th European Test Symposium, 2007

2006
CEDA: Control-flow Error Detection through Assertions.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006


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