Rajesh Galivanche

According to our database, Rajesh Galivanche authored at least 22 papers between 1989 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST.

Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche

IEEE Trans. Very Large Scale Integr. Syst., 2017

New Approaches for Power Binning of High Performance Microprocessors.

Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche

IEEE Trans. Computers, 2017

2016

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.

Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche

IEEE Trans. Computers, 2016

2014

Power droop reduction during Launch-On-Shift scan-based logic BIST.

Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.

Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche

J. Electron. Test., 2013

2012

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors.

Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris

IEEE Trans. Computers, 2012

2011

Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems.

Cecilia Metra, Rajesh Galivanche

IEEE Trans. Computers, 2011

2010

Path coverage based functional test generation for processor marginality validation.

Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche

Proceedings of the 2011 IEEE International Test Conference, 2010

Bridging pre-silicon verification and post-silicon validation.

Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor

Proceedings of the 47th Design Automation Conference, 2010

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.

Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

The Challenges of Nanotechnology and Gigacomplexity.

Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp

IEEE Des. Test Comput., 2009

2008

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.

Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche

Proceedings of the 13th European Test Symposium, 2008

A low-cost concurrent error detection technique for processor control logic.

Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Testing in the year 2020.

Rajesh Galivanche, Rohit Kapur, Antonio Rubio

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Test Roles in Diagnosis and Silicon Debug.

Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera

Proceedings of the 16th Asian Test Symposium, 2007

2006

Session Abstract.

Rajesh Galivanche, Bob Gottlieb

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005

Is the concern for soft-error overblown?

Rajesh Galivanche

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Trends in manufacturing test methods and their implications.

Sandip Kundu, T. M. Mak, Rajesh Galivanche

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Circuit and Platform Design Challenges in Technologies beyond 90nm.

Bill Grundmann, Rajesh Galivanche, Sandip Kundu

Proceedings of the 2003 Design, 2003

2001

Test Challenges in Nanometer Technologies.

Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche

J. Electron. Test., 2001

2000

Test challenges in nanometer technologies.

Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche

Proceedings of the 5th European Test Workshop, 2000

1989

An automatic test pattern generation program for large ASICs.

Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989