Régis Cattenoz

According to our database, Régis Cattenoz authored at least 5 papers between 2005 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Multi-Electroanalytical Method Capable, Duty-Cycled, 0.36 mm² Electrochemical Frontend, Achieving 170dB Current Sensing Range with Extended Compliance Voltage Adopting Feedforward Cancellation.

Amrith Sukumaran, Francesco Caruso, Régis Cattenoz, B. Putter, Jean-Luc Nagel, R. Ravanilla, I. Stergiou, G. Bouilly, P. Nussbaum, Stéphane Emery

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2021

A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge.

Petar Jokic, Erfan Azarkhish, Régis Cattenoz, Engin Türetken, Luca Benini, Stéphane Emery

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.

Enric M. Calvo, Philippe Renevey, Mathieu Lemay, Andrea Bonetti, Marc Pons Solé, Régis Cattenoz, Stéphane Emery, Ricard Delgado-Gonzalo

Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2006

Single-chip CMOS pulse generator for UWB systems.

Lydi Smaini, Carlo Tinella, Didier Hélal, Claude Stoecklin, Laurent Chabert, Christophe Devaucelle, Régis Cattenoz, Nils Rinaldi, Didier Belot

IEEE J. Solid State Circuits, 2006

2005

Single-chip CMOS pulse generator for UWB systems.

Lydi Smaini, Carlo Tinella, Didier Helal, Claude Stoecklin, Laurent Chabert, Christophe Devaucelle, Régis Cattenoz, Didier Belot

Proceedings of the 31st European Solid-State Circuits Conference, 2005