Marc Pons
Orcid: 0000-0002-1502-1192Affiliations:
- Swiss Center for Electronics and Microtechnology (CSEM), Neuchâtel, Switzerland
- Polytechnic University of Catalonia, Department of Electronic Engineering, Barcelona, Spain (former, PhD 2012)
According to our database1,
Marc Pons
authored at least 17 papers
between 2007 and 2022.
Collaborative distances:
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Bibliography
2022
ACM Trans. Embed. Comput. Syst., September, 2022
2021
Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Single-Battery Cooperative Sensors For Multi-Lead Long Term Ambulatory ECG Measurement.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
2019
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
WiseTOP: a quality of service-aware low power acquisition and wireless communication platform for prosthesis control.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2013
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Design of complex circuits using the Via-Configurable transistor array regular layout fabric.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007