Jean-Luc Nagel
According to our database1,
Jean-Luc Nagel
authored at least 21 papers
between 2000 and 2019.
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Bibliography
2019
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2013
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.
J. Low Power Electron., 2010
2009
IEEE J. Solid State Circuits, 2009
An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of the ESSCIRC 2008, 2008
2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.
J. Low Power Electron., 2005
2004
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.
Proceedings of the Integrated Circuit and System Design, 2004
2003
Proceedings of the Image Processing: Algorithms and Systems II, 2003
2002
Proceedings of the 11th European Signal Processing Conference, 2002
Proceedings of the 11th European Signal Processing Conference, 2002
2000
Proceedings of the 10th European Signal Processing Conference, 2000