Régis Cattenoz
According to our database1,
Régis Cattenoz authored at least 7 papers
between 2005 and 2026.
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Bibliography
2026
Hardware-Software co-design of FETA: a Flexible Low Power AI accelerator for Time-series signals.
Proceedings of the 24th Annual International Conference on Mobile Systems, 2026
Hardware-Algorithm Co-Design of a CORDIC-based Nonlinear Unit for low-power edge RNN inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
Multi-Electroanalytical Method Capable, Duty-Cycled, 0.36 mm<sup>2</sup> Electrochemical Frontend, Achieving 170dB Current Sensing Range with Extended Compliance Voltage Adopting Feedforward Cancellation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2021
A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
2006
2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005