Richard Joseph DeSantis

According to our database, Richard Joseph DeSantis authored at least 3 papers between 2009 and 2010.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2010

An Embedded All-Digital Circuit to Measure PLL Response.

Dennis Michael Fischette, Alvin Leng Sun Loke, Richard Joseph DeSantis, Gerry R. Talbot

IEEE J. Solid State Circuits, 2010

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.

Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI.

Dennis Michael Fischette, Richard Joseph DeSantis, John H. Lee

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009