Charles Lin Wang

According to our database, Charles Lin Wang authored at least 4 papers between 2009 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.

Alvin Leng Sun Loke, Bruce Andrew Doyle, Sanjeev K. Maheshwari, Dennis Michael Fischette, Charles Lin Wang, Tin Tin Wee, Emerson S. Fang

IEEE J. Solid State Circuits, 2012

2011

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors.

Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.

Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Loopback architecture for wafer-level at-speed testing of embedded HyperTransport^TM processor links.

Alvin Leng Sun Loke, Bruce Andrew Doyle, Michael M. Oshima, Wade L. Williams, Robert G. Lewis, Charles Lin Wang, Audie Hanpachern, Karen M. Tucker, Prashanth Gurunath, Gladney C. Asada, Chad O. Lackey, Tin Tin Wee, Emerson S. Fang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009