Alvin Leng Sun Loke

According to our database1, Alvin Leng Sun Loke authored at least 13 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2020
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

Nanoscale CMOS Implications on Analog/Mixed-Signal Design.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2012
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.
IEEE J. Solid State Circuits, 2012

Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2012

2011
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
An Embedded All-Digital Circuit to Measure PLL Response.
IEEE J. Solid State Circuits, 2010

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Loopback architecture for wafer-level at-speed testing of embedded HyperTransport<sup>TM</sup> processor links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006
A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking.
IEEE J. Solid State Circuits, 2006

2005


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