Emerson S. Fang

According to our database1, Emerson S. Fang authored at least 6 papers between 2009 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.
IEEE J. Solid State Circuits, 2012

2011
Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Loopback architecture for wafer-level at-speed testing of embedded HyperTransport<sup>TM</sup> processor links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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