Robert P. Kurshan

According to our database1, Robert P. Kurshan authored at least 63 papers between 1972 and 2018.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of two.

Timeline

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Bibliography

2018
Transfer of Model Checking to Industrial Practice.
Proceedings of the Handbook of Model Checking., 2018

2010
The Localization Reduction and Counterexample-Guided Abstraction Refinement.
Proceedings of the Time for Verification, 2010

2008
Verification Technology Transfer.
Proceedings of the 25 Years of Model Checking - History, Achievements, Perspectives, 2008

Application of Formal Word-Level Analysis to Constrained Random Simulation.
Proceedings of the Computer Aided Verification, 20th International Conference, 2008

2007
Scaling Commercial Verification to Larger Systems.
Proceedings of the Hardware and Software: Verification and Testing, 2007

2005
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
Minimal length test vectors for multiple-fault detection.
Theor. Comput. Sci., 2004

Lessons Learned from Model Checking a NASA Robot Controller.
Formal Methods in System Design, 2004

Formal verification as a technology transfer problem.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

Translating Software Designs for Model Checking.
Proceedings of the Fundamental Approaches to Software Engineering, 2004

Evolution of Model Checking into the EDA Industry.
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

2003
Experimental Analysis of Different Techniques for Bounded Model Checking.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2003

Translation-Based Compositional Reasoning for Software Systems.
Proceedings of the FME 2003: Formal Methods, 2003

2002
Combining Software and Hardware Verification Techniques.
Formal Methods in System Design, 2002

Model Checking and Abstraction.
Proceedings of the Abstraction, 2002

Compressing Transitions for Model Checking.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Which Branching-Time Properties are Effectively Linear?
J. Log. Comput., 2001

A New Heuristic for Bad Cycle Detection Using BDDs.
Formal Methods in System Design, 2001

A Formal Object-Oriented Analysis for Software Reliability: Design for Verification.
Proceedings of the Fundamental Approaches to Software Engineering, 2001

A Practical Approach to Coverage in Model Checking.
Proceedings of the Computer Aided Verification, 13th International Conference, 2001

Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams.
Proceedings of the Computer Aided Verification, 13th International Conference, 2001

2000
The Evolution of Commercial Formal Verification.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Model Checking Synchronous Timing Diagrams.
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Syntactic Program Transformations for Automatic Abstraction.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

PET: An Interactive Software Testing Tool.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999
Efficient Analysis of Cyclic Definitions.
Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998
Static Partial Order Reduction.
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1998

Membership Questions for Timed and Hybrid Automata.
Proceedings of the 19th IEEE Real-Time Systems Symposium, 1998

1997
Verifying hardware in its software context.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Verifying VHDL Designs with COSPAN.
Proceedings of the Formal Hardware Verification - Methods and Systems in Comparison, 1997

Formal Verification in a Commercial Setting.
Proceedings of the 34st Conference on Design Automation, 1997

Existence of Reduction Hierarchies.
Proceedings of the Computer Science Logic, 11th International Workshop, 1997

Model checking without hardware drivers.
Proceedings of the Advances in Hardware Design and Verification, 1997

1996
Verifying Abstractions of Timed Systems.
Proceedings of the CONCUR '96, 1996

1995
Testing Language Containment for omega-Automata Using BDD's
Inf. Comput., April, 1995

Timing Verification by Successive Approximation
Inf. Comput., April, 1995

A Structural Induction Theorem for Processes
Inf. Comput., February, 1995

Timing Analysis in COSPAN.
Proceedings of the Hybrid Systems III: Verification and Control, 1995

Modelling Asynchrony with a Synchronous Model.
Proceedings of the Computer Aided Verification, 1995

1994
The complexity of verification.
Proceedings of the Twenty-Sixth Annual ACM Symposium on Theory of Computing, 1994

How Linear Can Branching-Time Be?
Proceedings of the Temporal Logic, First International Conference, 1994

Models Whose Checks Don't Explode.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993
A Unified Approch for Showing Language Inclusion and Equivalence Between Various Types of omega-Automata.
Inf. Process. Lett., 1993

A Unified Approach to Language Containment and Fair CTL Model Checking.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

A Structural Linearization Principle for Processes.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

Verification of a Multiplier: 64 Bits and Beyond.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

BDD-Based Debugging Of Design Using Language Containment and Fair CTL.
Proceedings of the Computer Aided Verification, 5th International Conference, 1993

1992
Efficient omega-Regular Language Containment.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

Timing Verification by Successive Approximation.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991
Analysis of digital circuits through symbolic reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

1990
Preface.
Proceedings of the Computer-Aided Verification, 1990

Task-Driven Supervisory Control of Discrete Event Systems.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

A Unified Approach For Showing Language Containment And Equivalence Between Various Types Of Omega-Automata.
Proceedings of the CAAP '90, 1990

1989
Analysis of Discrete Event Coordination.
Proceedings of the Stepwise Refinement of Distributed Systems, 1989

Extensions of Temporal Logic for Counting with Applications to Model Verification.
Proceedings of the Protocol Specification, 1989

A Structural Induction Theorem for Processes.
Proceedings of the Eighth Annual ACM Symposium on Principles of Distributed Computing, 1989

A Synthesis of Two Approaches for Verifying Finite State Concurrent Systems.
Proceedings of the Logic at Botik '89, 1989

1987
Complementing Deterministic Büchi Automata in Polynomial Time.
J. Comput. Syst. Sci., 1987

1984
Automated Implementation from Formal Specification.
Proceedings of the Protocol Specification, 1984

1983
A Language for the Specification and Analysis of Protocols.
Proceedings of the Protocol Specification, Testing, and Verification, III, Proceedings of the IFIP WG 6.1 Third International Workshop on Protocol Specification, Testing and Verification, organized by IBM Research, Rüschlikon, Switzerland, 31 May, 1983

A Calculus for Protocol Specification and Validation.
Proceedings of the Protocol Specification, Testing, and Verification, III, Proceedings of the IFIP WG 6.1 Third International Workshop on Protocol Specification, Testing and Verification, organized by IBM Research, Rüschlikon, Switzerland, 31 May, 1983

Modelling Elapsed Time in Protocol Specification.
Proceedings of the Protocol Specification, Testing, and Verification, III, Proceedings of the IFIP WG 6.1 Third International Workshop on Protocol Specification, Testing and Verification, organized by IBM Research, Rüschlikon, Switzerland, 31 May, 1983

1972
Coset Analysis of Reed Muller Codes Via Translates of Finite Vector Spaces
Information and Control, June, 1972


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