Andreas Kuehlmann

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Property Directed Reachability for QF_BV with mixed type atomic reasoning units.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

QF BV model checking with property directed reachability.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Hardware Acceleration for Constraint Solving for Random Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

The Technology and Psychology of Testing Your Code as You Develop It.

[BibT_eX]

[DOI]

Proceedings of the Tests and Proofs - 6th International Conference, 2012

Generalized SAT-sweeping for post-mapping optimization.

[BibT_eX]

[DOI]

Smita Krishnaswamy

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Integrated logic synthesis using simulated annealing.

[BibT_eX]

[DOI]

Petra Färm

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

An approach for dynamic selection of synthesis transformations based on Markov Decision Processes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Are logic synthesis tools robust?

[BibT_eX]

[DOI]

Alberto Puggelli

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 48th Design Automation Conference, 2011

2010

Does IC design have a future in the clouds?

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

SAT-based protein design.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Guess, solder, measure, repeat: how do I get my mixed-signal chip right?

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

EDA in flux: should I stay or should I go?

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Generalizing DPLL to Richer Logics.

[BibT_eX]

[DOI]

Kenneth L. McMillan

Mooly Sagiv

Proceedings of the Computer Aided Verification, 21st International Conference, 2009

A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008

Next generation wireless-multimedia devices: who is up for the challenge?

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Verifying really complex systems: on earth and beyond.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Stimulus generation for constrained random simulation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On Resolution Proofs for Combinational Equivalence.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Fast Boolean Matching with Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Building a better Boolean matcher and symmetry detector.

[BibT_eX]

[DOI]

Donald Chai

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

SAT sweeping with local observability don't-cares.

[BibT_eX]

[DOI]

Qi Zhu

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 43rd Design Automation Conference, 2006

2005

A fast pseudo-Boolean constraint solver.

[BibT_eX]

[DOI]

Donald Chai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Early research experience with OpenAccess gear: an open source development environment for physical design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Temporal Decomposition for Logic Optimization.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2005

Logic optimization using rule-based randomized search.

[BibT_eX]

[DOI]

Petra Färm

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Design Automation TC Newsletter.

[BibT_eX]

John Willis

IEEE Des. Test Comput., 2004

Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation.

[BibT_eX]

[DOI]

Donald Chai

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Dynamic transition relation simplification for bounded property checking.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Physical placement driven by sequential timing analysis.

[BibT_eX]

[DOI]

Aaron P. Hurst

Philip Chong

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Scalable Automated Verification via Expert-System Guided Transformations.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

Enhanced Diameter Bounding via Structural.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation.

[BibT_eX]

[DOI]

René Krenz

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Structural Detection of Symmetries in Boolean Functions.

[BibT_eX]

[DOI]

Guoqiang Wang

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Multi-Domain Clock Skew Scheduling.

[BibT_eX]

[DOI]

Kaushik Ravindran

Ellen Sentovich

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

CAMA: A Multi-Valued Satisfiability Solver.

[BibT_eX]

[DOI]

Cong Liu

Matthew W. Moskewicz

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Robust Boolean reasoning for equivalence checking and functional property verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Minimum-power retiming for dual-supply CMOS circuits.

[BibT_eX]

[DOI]

Farhana Sheikh

Kurt Keutzer

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis.

[BibT_eX]

[DOI]

HoonSang Jin

Fabio Somenzi

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2002

Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.

[BibT_eX]

René Krenz

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Property Checking via Structural Analysis.

[BibT_eX]

[DOI]

Jacob A. Abraham

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001

SIVA: A System for Coverage-Directed State Space Search.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

Design Of Provably Correct Storage Arrays.

[BibT_eX]

[DOI]

Rajiv V. Joshi

Wei Hwang

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Sequential SPFDs.

[BibT_eX]

[DOI]

Subarnarekha Sinha

Robert K. Brayton

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Will Nanotechnology Change the Way We Design and Verify Systems? (Panel).

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Min-Area Retiming on Dynamic Circuit Structures.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Circuit-based Boolean Reasoning.

[BibT_eX]

[DOI]

Malay K. Ganai

Viresh Paruthi

Proceedings of the 38th Design Automation Conference, 2001

Transformation-Based Verification Using Generalized Retiming.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

2000

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation.

[BibT_eX]

[DOI]

Viresh Paruthi

Sérgio Vale Aguiar Campos

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

Model Checking Semi-Continuous Time Models Using BDDs.

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Symbolic Model Checking, 1999

Probabilistic state space search.

[BibT_eX]

[DOI]

Kenneth L. McMillan

Robert K. Brayton

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Enhancing Simulation with BDDs and ATPG.

[BibT_eX]

[DOI]

Malay K. Ganai

Adnan Aziz

Proceedings of the 36th Conference on Design Automation, 1999

1997

Equivalence Checking Using Cuts and Heaps.

[BibT_eX]

[DOI]

Florian Krohm

Proceedings of the 34st Conference on Design Automation, 1997

1996

The use of random simulation in formal verification.

[BibT_eX]

[DOI]

Florian Krohm

Arjen Mets

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

Verity - A formal verification program for custom CMOS circuits.

[BibT_eX]

[DOI]

Arvind Srinivasan

David P. LaPotin

IBM J. Res. Dev., 1995

High-level synthesis in an industrial environment.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 1995

1994

Grammar-Based Optimization of Synthesis Scenarios.

[BibT_eX]

[DOI]

Lukas P. P. P. van Ginneken

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Error Diagnosis for Transistor-Level Verification.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

A system for production use of high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1993

1992

High-Level State Machine Specification and Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Timing analysis in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Control Optimization in High-Level Synthesis Using Behavioral Don't Cares.

[BibT_eX]

[DOI]

Donald A. Lobo