Andreas Kuehlmann

According to our database1, Andreas Kuehlmann authored at least 65 papers between 1992 and 2017.

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Awards

IEEE Fellow

IEEE Fellow 2003, "For the development of formal equivalence checking technology and its successful application to microprocessor and ASIC designs.".

Timeline

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Bibliography

2017
Panel: Building a Business around Secure Development.
Proceedings of the IEEE Cybersecurity Development, SecDev 2017, Cambridge, MA, USA, 2017

2014
Property directed invariant refinement for program verification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Property Directed Reachability for QF_BV with mixed type atomic reasoning units.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
QF BV model checking with property directed reachability.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Hardware Acceleration for Constraint Solving for Random Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

The Technology and Psychology of Testing Your Code as You Develop It.
Proceedings of the Tests and Proofs - 6th International Conference, 2012

Generalized SAT-sweeping for post-mapping optimization.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Integrated logic synthesis using simulated annealing.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

An approach for dynamic selection of synthesis transformations based on Markov Decision Processes.
Proceedings of the Design, Automation and Test in Europe, 2011

Are logic synthesis tools robust?
Proceedings of the 48th Design Automation Conference, 2011

2010
Does IC design have a future in the clouds?
Proceedings of the 47th Design Automation Conference, 2010

2009
SAT-based protein design.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Proceedings of the 46th Design Automation Conference, 2009

EDA in flux: should I stay or should I go?
Proceedings of the 46th Design Automation Conference, 2009

Generalizing DPLL to Richer Logics.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008
Next generation wireless-multimedia devices: who is up for the challenge?
Proceedings of the 45th Design Automation Conference, 2008

Verifying really complex systems: on earth and beyond.
Proceedings of the 45th Design Automation Conference, 2008

2007
Stimulus generation for constrained random simulation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On Resolution Proofs for Combinational Equivalence.
Proceedings of the 44th Design Automation Conference, 2007

2006
Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Fast Boolean Matching with Don't Cares.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Building a better Boolean matcher and symmetry detector.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

SAT sweeping with local observability don't-cares.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A fast pseudo-Boolean constraint solver.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Early research experience with OpenAccess gear: an open source development environment for physical design.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Temporal Decomposition for Logic Optimization.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

Logic optimization using rule-based randomized search.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Design Automation TC Newsletter.
IEEE Des. Test Comput., 2004

Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Dynamic transition relation simplification for bounded property checking.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Physical placement driven by sequential timing analysis.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Scalable Automated Verification via Expert-System Guided Transformations.
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

Enhanced Diameter Bounding via Structural.
Proceedings of the 2004 Design, 2004

2003
Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Structural Detection of Symmetries in Boolean Functions.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Multi-Domain Clock Skew Scheduling.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

CAMA: A Multi-Valued Satisfiability Solver.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Robust Boolean reasoning for equivalence checking and functional property verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Minimum-power retiming for dual-supply CMOS circuits.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2002

Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Property Checking via Structural Analysis.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
SIVA: A System for Coverage-Directed State Space Search.
J. Electron. Test., 2001

Design Of Provably Correct Storage Arrays.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Sequential SPFDs.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Will Nanotechnology Change the Way We Design and Verify Systems? (Panel).
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Min-Area Retiming on Dynamic Circuit Structures.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Circuit-based Boolean Reasoning.
Proceedings of the 38th Design Automation Conference, 2001

Transformation-Based Verification Using Generalized Retiming.
Proceedings of the Computer Aided Verification, 13th International Conference, 2001

2000
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Model Checking Semi-Continuous Time Models Using BDDs.
Electron. Notes Theor. Comput. Sci., 1999

Probabilistic state space search.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Enhancing Simulation with BDDs and ATPG.
Proceedings of the 36th Conference on Design Automation, 1999

1997
Equivalence Checking Using Cuts and Heaps.
Proceedings of the 34st Conference on Design Automation, 1997

1996
The use of random simulation in formal verification.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995
Verity - A formal verification program for custom CMOS circuits.
IBM J. Res. Dev., 1995

High-level synthesis in an industrial environment.
IBM J. Res. Dev., 1995

1994
Grammar-Based Optimization of Synthesis Scenarios.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Error Diagnosis for Transistor-Level Verification.
Proceedings of the 31st Conference on Design Automation, 1994

1993
A system for production use of high-level synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 1993

1992
High-Level State Machine Specification and Synthesis.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Timing analysis in high-level synthesis.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Control Optimization in High-Level Synthesis Using Behavioral Don't Cares.
Proceedings of the 29th Design Automation Conference, 1992


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