Sandeep K. Shukla

According to our database1, Sandeep K. Shukla authored at least 238 papers between 1996 and 2020.

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Bibliography

2020
TECS Editorial: Rethinking and Re-evaluating in the Time of Crisis.
ACM Trans. Embedded Comput. Syst., 2020

Editorial: Embedded Computing and Society.
ACM Trans. Embedded Comput. Syst., 2020

Approaches for Assigning Offsets to Signals for Improving Frame Packing in CAN-FD.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2020

Detecting Malicious Accounts on the Ethereum Blockchain with Supervised Learning.
Proceedings of the Cyber Security Cryptography and Machine Learning, 2020

2019
Machine learning in cybersecurity: A review.
Wiley Interdiscip. Rev. Data Min. Knowl. Discov., 2019

Editorial: Adversaries and Robustness.
ACM Trans. Embedded Comput. Syst., 2019

Editorial: Reflections on the History of Cyber-Physical versus Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2019

Editorial: Human Factors in Embedded Computing.
ACM Trans. Embedded Comput. Syst., 2019

Editorial: Embedded Security Challenge: Cyber Security Contests in the Embedded Computing Domain.
ACM Trans. Embedded Comput. Syst., 2019

LFSR based versatile divider architectures for BCH and RS error correction encoders.
Microprocess. Microsystems, 2019

Asynchronous hardware implementations for crypto primitives.
Microprocess. Microsystems, 2019

Sequence to sequence deep learning models for solar irradiation forecasting.
CoRR, 2019

Verity: Blockchains to Detect Insider Attacks in DBMS.
CoRR, 2019

Automated Classification of Web-Application Attacks for Intrusion Detection.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019

Formal Hardware Verification of InfoSec Primitives.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Study of Inequality in the Ethereum Smart Contract Ecosystem.
Proceedings of the Sixth International Conference on Internet of Things: Systems, 2019

Vulnerability Assessment and Mitigation for Industrial Critical Infrastructures with Cyber Physical Test Bed.
Proceedings of the IEEE International Conference on Industrial Cyber Physical Systems, 2019

Evading API Call Sequence Based Malware Classifiers.
Proceedings of the Information and Communications Security - 21st International Conference, 2019

Malware Classification Using Image Representation.
Proceedings of the Cyber Security Cryptography and Machine Learning, 2019

PeerClear: Peer-to-Peer Bot-net Detection.
Proceedings of the Cyber Security Cryptography and Machine Learning, 2019

2018
Interfacing Power System and ICT Simulators: Challenges, State-of-the-Art, and Case Studies.
IEEE Trans. Smart Grid, 2018

Editorial: Need for Artifact Verified Articles in ACM Transactions.
ACM Trans. Embedded Comput. Syst., 2018

Editorial: Early Career Researchers in Embedded Computing.
ACM Trans. Embedded Comput. Syst., 2018

Editorial: To Use or Not To? Embedded Systems for Voting.
ACM Trans. Embedded Comput. Syst., 2018

Editorial: Industry 4.0 - A Confluence of Embedded Artificial Intelligence, Machine Learning, Robotics and Security.
ACM Trans. Embedded Comput. Syst., 2018

Editorial: Trust and Security Must Become a Primary Design Concern in Embedded Computing.
ACM Trans. Embedded Comput. Syst., 2018

Low power hardware implementations for network packet processing elements.
Integr., 2018

Partitioned security processor architecture on FPGA platform.
IET Comput. Digit. Tech., 2018

Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017
Editorial: Security of Mobile Devices.
ACM Trans. Embedded Comput. Syst., 2017

Editorial: Cyber Security, IoT, Block Chains - Risks and Opportunities.
ACM Trans. Embedded Comput. Syst., 2017

Editorial: Continuing the Course.
ACM Trans. Embedded Comput. Syst., 2017

Flexible VLSI architectures for Galois field multipliers.
Integr., 2017

A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Flexible Composite Galois Field GF((2^m)^2) Multiplier Designs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Offset Assignment to Signals for Improving Frame Packing in CAN-FD.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

The Multi-Domain Frame Packing Problem for CAN-FD.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

2016
Editorial: Distributed Public Ledgers and Block Chains - What Good Are They for Embedded Systems?
ACM Trans. Embedded Comput. Syst., 2016

Editorial: Security of Embedded Systems and Cyber Irons - Embedded Systems for Security.
ACM Trans. Embedded Comput. Syst., 2016

Editorial: Fence Itself Grazing the Field - Security from the Sentries.
ACM Trans. Embedded Comput. Syst., 2016

Editorial: Science of the Big and Small and Embedded Computing Systems.
ACM Trans. Embedded Comput. Syst., 2016

A Survey of Automatic Protocol Reverse Engineering Tools.
ACM Comput. Surv., 2016

Cyber Security of Cyber Physical Systems: Cyber Threats and Defense of Critical Infrastructures.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Hardware optimizations for crypto implementations (Invited paper).
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Design space exploration for deterministic ethernet-based architecture of automotive systems.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2015
Editorial: Big Data, Internet of Things, Cybersecurity - A New Trinity of Embedded Systems Research.
ACM Trans. Embedded Comput. Syst., 2015

Editorial: Schizoid Design for Critical Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2015

Editorial: Oh Security - Where Art Thou?
ACM Trans. Embedded Comput. Syst., 2015

Editorial: Regular, Special, and Related Issues.
ACM Trans. Embedded Comput. Syst., 2015

Optimization of Latency Insensitive Systems Through Back Pressure Minimization.
IEEE Trans. Computers, 2015

Design of Cyber Security for Critical Infrastructures: A Case for a Schizoid Design Approach.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015

Mapping functional behavior onto architectural model in a model driven embedded system design.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Towards refinement types for time-dependent data-flow networks.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

The challenge of interoperability: model-based integration for automotive control software.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Editorial: Diversity Galore & A Call for Resilient, Sustainable and Secure System Design.
ACM Trans. Embedded Comput. Syst., 2014

Editorial: Embedded systems - more than methodology.
ACM Trans. Embedded Comput. Syst., 2014

Editorial: Embedded, Cyber-Physical, Hybrid...
ACM Trans. Embedded Comput. Syst., 2014

Editorial: Embedded everywhere for everyone.
ACM Trans. Embedded Comput. Syst., 2014

Constructive polychronous systems.
Sci. Comput. Program., 2014

Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions.
Design Autom. for Emb. Sys., 2014

Towards an Architecture-Centric Approach Dedicated to Model-Based Virtual Integration for Embedded Software Systems.
Proceedings of the First International Workshop on Architecture Centric Virtual Integration co-located with the 17th International Conference on Model Driven Engineering Languages and Systems, 2014

Construction of a microgrid communication network.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014

Compiling polychronous programs into conditional partial orders for ASIP synthesis.
Proceedings of the 2nd FME Workshop on Formal Methods in Software Engineering, 2014

APECS code synthesis: Extending ocarina for multi-threaded code synthesis from AADL models for Safety Critical applications.
Proceedings of 11th IEEE International Conference on Networking, Sensing and Control, 2014

Verification of unit and dimensional consistencies in polychronous specifications.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013
Embedding Polychrony into Synchrony.
IEEE Trans. Software Eng., 2013

Abstraction of polychronous dataflow specifications into mode-automata.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

A Distributed Real-Time Event Correlation Architecture for SCADA Security.
Proceedings of the Critical Infrastructure Protection VII, 2013

On Model-Based Software Development.
Proceedings of the Perspectives on the Future of Software Engineering, 2013

Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A New Multi-threaded Code Synthesis Methodology and Tool for Correct-by-Construction Synthesis from Polychronous Specifications.
Proceedings of the 13th International Conference on Application of Concurrency to System Design, 2013

2012
GECO: Global Event-Driven Co-Simulation Framework for Interconnected Power System and Communication Network.
IEEE Trans. Smart Grid, 2012

Vulnerabilities and Countermeasures - A Survey on the Cyber Security Issues in the Transmission Subsystem of a Smart Grid.
J. Cyber Secur. Mobil., 2012

Formal Verification of Hierarchically Distributed Agent Based Protection Scheme in Smart Grid.
Proceedings of the Model Checking Software - 19th International Workshop, 2012

Cyber security impacts on all-PMU state estimator - a case study on co-simulation platform GECO.
Proceedings of the IEEE Third International Conference on Smart Grid Communications, 2012

Communication network modeling and simulation for Wide Area Measurement applications.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2012

A detailed analysis of the effective-load-carrying-capacity behavior of plug-in electric vehicles in the power grid.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2012

Accelerating SystemC simulations using GPUs.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis.
Springer, ISBN: 978-1-4614-0871-0, 2012

2011
Guest Editors' Introduction: Special Section on Science of Design for Safety Critical Systems.
IEEE Trans. Computers, 2011

Challenges of Rapidly Emerging Consumer Space Multiprocessors.
IEEE Des. Test Comput., 2011

A Brief History of Multiprocessors and EDA.
IEEE Des. Test Comput., 2011

Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models.
IEEE Des. Test Comput., 2011

SMT based false causal loop detection during code synthesis from Polychronous specifications.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

High Level Power Estimation Models for FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Integrating system descriptions by clocked guarded actions.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

2010
Power Aware High Level Synthesis of Hardware Coprocessors.
J. Low Power Electron., 2010

Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus.
J. Electronic Testing, 2010

A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Minimizing back pressure for latency insensitive system synthesis.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Translating concurrent action oriented specifications to synchronous guarded actions.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Coprocessor design space exploration using high level synthesis.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Optimization of back pressure and throughput for latency insensitive systems.
Proceedings of the 28th International Conference on Computer Design, 2010

System level simulation guided approach to improve the efficacy of clock-gating.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

SCGPSim: a fast SystemC simulator on GPUs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

An alternative polychronous model and synthesis methodology for model-driven embedded software.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism.
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

The Model Checking View to Clock Gating and Operand Isolation.
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

MRICDF: A Polychronous Model for Embedded Software Synthesis.
Proceedings of the Synthesis of Embedded Software, 2010

Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications.
Springer, ISBN: 978-1-4419-6480-9, 2010

2009
A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications.
J. Low Power Electron., 2009

<i>SCoPE</i>: Statistical Regression Based Power Models for Co-Processors Power Estimation.
J. Low Power Electron., 2009

Guest editorial: IEEE/ACM symposium on nanoscale architectures (NANOARCH07).
ACM J. Emerg. Technol. Comput. Syst., 2009

Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework.
Electron. Notes Theor. Comput. Sci., 2009

Preface.
Electron. Notes Theor. Comput. Sci., 2009

An Analysis of the Composition of Synchronous Systems.
Electron. Notes Theor. Comput. Sci., 2009

Generating Multi-Threaded code from Polychronous Specifications.
Electron. Notes Theor. Comput. Sci., 2009

Metamodeling: What is it good for?
IEEE Des. Test Comput., 2009

Metamodeling: An Emerging Representation Paradigm for System-Level Design.
IEEE Des. Test Comput., 2009

Hardware Coprocessor Synthesis from an ANSI C Specification.
IEEE Des. Test Comput., 2009

Expressing the Behavior of Three Very Different Concurrent Systems by Using Natural Extensions of Separation Logic
Proceedings of the Proceedings 16th International Workshop on Expressiveness in Concurrency, 2009

Model-Driven Engineering and Safety-Critical Embedded Software.
IEEE Computer, 2009

Accurate power estimation of hardware co-processors using system level simulation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Power estimation methodology for a high-level synthesis framework.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Distributed Simulation of AADL Specifications in a Polychronous Model of Computation.
Proceedings of the International Conference on Embedded Software and Systems, 2009

MCBCG: Model Checking Based Sequential Clock-Gating.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study.
Proceedings of the FM 2009: Formal Methods, 2009

EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications.
Proceedings of the Forum on specification and Design Languages, 2009

Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design.
Artech House, ISBN: 978-1-59693-424-5, 2009

2008
A Trace-Based Framework for Verifiable GALS Composition of IPs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models.
IEEE Trans. Very Large Scale Integr. Syst., 2008

MMV: A Metamodeling Based Microprocessor Validation Environment.
IEEE Trans. Very Large Scale Integr. Syst., 2008

On Cosimulating Multiple Abstraction-Level System-Level Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Dataflow Architectures for GALS.
Electron. Notes Theor. Comput. Sci., 2008

Model-Driven Validation of SystemC Designs.
EURASIP J. Embed. Syst., 2008

C-Based Design of Heterogeneous Embedded Systems.
EURASIP J. Embed. Syst., 2008

Mining metadata for composability of IPs from SystemC IP library.
Design Autom. for Emb. Sys., 2008

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system.
Design Autom. for Emb. Sys., 2008

Verifying Compiler Based Refinement of BluespecTM.
Proceedings of the Model Checking Software, 2008

Applying Verification Collaterals for Accurate Power Estimation.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Formal Transformation of a KPN Specification to a GALS Implementation.
Proceedings of the Forum on specification and Design Languages, 2008

Ingredients for Successful System Level Design Methodology.
Springer, ISBN: 978-1-4020-8471-3, 2008

2007
EWD: A metamodeling driven customizable multi-MoC system modeling framework.
ACM Trans. Design Autom. Electr. Syst., 2007

Reliability Analysis of Large Circuits Using Scalable Techniques and Tools.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Heterogeneous Behavioral Hierarchy Extensions for SystemC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Algorithms for power savings.
ACM Trans. Algorithms, 2007

Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications.
J. Low Power Electron., 2007

Algorithms for low power hardware synthesis from Concurrent Action Oriented Specifications (CAOS).
IJES, 2007

Guest Editors' Introduction: GALS Design and Validation.
IEEE Des. Test Comput., 2007

Model Based Test Generation for Microprocessor Architecture Validation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Scalable techniques and tools for reliability analysis of large circuits.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Model Checking Bluespec Specified Hardware Designs.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Assertion-Based Modal Power Estimation.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

VT Matrix Multiply Design for MEMOCODE '07.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Type Inference for IP Composition.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Local Causal Reasoning of a Safety-Critical Subway System.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Model-driven test generation for system level validation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Metamodeling based Framework for Architectural Modeling and Simulator Generation.
Proceedings of the Forum on specification and Design Languages, 2007

Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design fault directed test generation for microprocessor validation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

2006
CARH: service-oriented architecture for validating system-level designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Validating Families of Latency Insensitive Protocols.
IEEE Trans. Computers, 2006

Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems.
Formal Methods Syst. Des., 2006

A Functional Programming Framework for Latency Insensitive Protocol Validation.
Electron. Notes Theor. Comput. Sci., 2006

Preface.
Electron. Notes Theor. Comput. Sci., 2006

Guest Editors' Introduction: The True State of the Art of ESL Design.
IEEE Des. Test Comput., 2006

A Trace Based Framework for Validation of SoC Designs with GALS Systems.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

SoC Design Space Exploration through Automated IP Selection from SystemC IP Library.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Low-power hardware synthesis from TRS-based specifications.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Panel: Nano-computing - do we need new formal approaches?
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Polychronous Methodology For System Design: A True Concurrency Approach.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Panel: Assertion-Based Verification -What's the Big Deal?
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

MMV: Metamodeling Based Microprocessor Valiation Environment.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

MCF: A Metamodeling-based Visual Component Composition Framework.
Proceedings of the Forum on specification and Design Languages, 2006

Design with race-free hardware semantics.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Heterogeneous behavioral hierarchy for system level designs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A hybrid framework for design and analysis of fault-tolerant architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Design Issues for Networked Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

An overview of the competitive and adversarial approaches to designing dynamic power management strategies.
IEEE Trans. Very Large Scale Integr. Syst., 2005

XFM: An incremental methodology for developing formal models.
ACM Trans. Design Autom. Electr. Syst., 2005

Guest editorial: Special issue on models and methodologies for co-design of embedded systems.
ACM Trans. Embedded Comput. Syst., 2005

Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Evaluating the reliability of NAND multiplexing with PRISM.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking.
Int. J. Parallel Program., 2005

Using probabilistic model checking for dynamic power management.
Formal Asp. Comput., 2005

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.
IEEE Des. Test Comput., 2005

Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

System Level Design Methodology for System On Chips using Multi-Threaded Graphs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Automated Extraction of Structural Information from SystemC-based IP for Validation.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Teaching Game Theory for Computer Engineering.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Extended abstract: a race-free hardware modeling language.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Improving SystemC simulation through Petri net reductions.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Automated clock inference for stream function-based system level specifications.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Towards Behavioural Hierarchy Extensions for SystemC.
Proceedings of the Forum on specification and Design Languages, 2005

Modelling Environment for Heterogeneous Systems based on MoCs.
Proceedings of the Forum on specification and Design Languages, 2005

SystemCXML: An Exstensible SystemC Front end Using XML.
Proceedings of the Forum on specification and Design Languages, 2005

An Introductory Survey of Networked Embedded Systems.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Formal Refinement Checking in a System-level Design Methodology.
Fundam. Inform., 2004

Preface.
Electron. Notes Theor. Comput. Sci., 2004

Panel Summaries.
IEEE Des. Test Comput., 2004

Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Extreme Formal Modeling (XFM) for Hardware Models.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Panel: given that hardware verification has been an uphill battle, what is the future of software verification?
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Effects of property ordering in an incremental formal modeling methodology.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A Functional Programming Framework of Heterogeneous Model of Computation for System Design.
Proceedings of the Forum on specification and Design Languages, 2004

Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks.
Proceedings of the 2004 Design, 2004

Modular design through component abstraction.
Proceedings of the 2004 International Conference on Compilers, 2004

A Behavioral Type Inference System for Compositional System-on-Chip Design.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

SystemC Kernel extensions for heterogeneous system modeling - a framework for multi-MoC modeling and simulation.
Kluwer, ISBN: 978-1-4020-8087-6, 2004

2003
Online strategies for dynamic power management in systems with multiple power-saving states.
ACM Trans. Embedded Comput. Syst., 2003

BALBOA: a component-based design environment for system models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation?
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

FORGE: A Framework for Optimization of Distributed Embedded Systems Software.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Formal Methods for Dynamic Power Management.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Nano, quantum, and molecular computing: are we ready for the validation and test challenges?
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Polychrony for Refinement-Based Design.
Proceedings of the 2003 Design, 2003

Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated.
Proceedings of the 2003 Design, 2003

Formal verification - prove it or pitch it.
Proceedings of the 40th Design Automation Conference, 2003

Typing abstractions and management in a component framework.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Polychrony for Formal Refinement-Checking in a System-Level Design Methodology.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

2002
Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Efficient Simulation of Synthesis-Oriented System Level Designs.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Formal analysis and validation of continuous-time Markov chain based system level power management strategies.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Using Aspect-GAMMA in the design of embedded systems.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Structured Component Composition Frameworks for Embedded System Design.
Proceedings of the High Performance Computing, 2002

Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation.
Proceedings of the 2002 Design, 2002

Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States.
Proceedings of the 2002 Design, 2002

An Environment for Dynamic Component Composition for Efficient Co-Design .
Proceedings of the 2002 Design, 2002

2001
A New Heuristic for Bad Cycle Detection Using BDDs.
Formal Methods Syst. Des., 2001

Interoperability as a design issue in C++ based modeling environments.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

A model checking approach to evaluating system level dynamic power management policies for embedded systems.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

1999
A Case Study in CORBA-based Event Management for Correlation Across Network Management Servers in a Centralized Network Operation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998
Unification and Matching in Process Algebras.
Proceedings of the Rewriting Techniques and Applications, 9th International Conference, 1998

1996
I/O Automata Based Verification of Finite State Distributed Systems: Complexity Issues (Abstract).
Proceedings of the Fifteenth Annual ACM Symposium on Principles of Distributed Computing, 1996

On the Complexity of Relational Problems for Finite State Processes (Extended Abstract).
Proceedings of the Automata, Languages and Programming, 23rd International Colloquium, 1996

A simulation and validation tool for self-stabilizing protocols.
Proceedings of the Spin Verification System, 1996

The polynomial time decidability of simulation relations for finite processes: A HORNSAT based approach.
Proceedings of the Satisfiability Problem: Theory and Applications, 1996

HORNSAT, Model Checking, Verification and games (Extended Abstract).
Proceedings of the Computer Aided Verification, 8th International Conference, 1996


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