Dragomir Milojevic

According to our database1, Dragomir Milojevic
  • authored at least 31 papers between 2005 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2017
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Energy minimization at all layers of the data center: The ParaDIME project.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

2014
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
Embedded Systems Letters, 2014

A context aware cache controller to bridge the gap between theory and practice in real-time systems.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

2013
Panel: "will 3D-IC remain a technology of the future... even in the future?".
Proceedings of the Design, Automation and Test in Europe, 2013

Design issues in heterogeneous 3D/2.5D integration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Thermal characterization of cloud workloads on a power-efficient server-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

U-EDF: An Unfair But Optimal Multiprocessor Scheduling Algorithm for Sporadic Tasks.
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

Techniques Optimizing the Number of Processors to Schedule Multi-threaded Tasks.
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

2011
Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC.
Signal Processing Systems, 2011

Swapping to reduce preemptions and migrations in EKG.
SIGBED Review, 2011

Reducing Preemptions and Migrations in Real-Time Multiprocessor Scheduling Algorithms by Releasing the Fairness.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
Proceedings of the Design, Automation and Test in Europe, 2011

DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's.
Proceedings of the ARCS '10, 2010

2009
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.
Signal Processing Systems, 2009

Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.
IEEE Trans. Computers, 2008

Design and Architectures for Signal and Image Processing.
EURASIP J. Emb. Sys., 2008

Power-Aware Real-Time Scheduling upon Identical Multiprocessor Platforms.
Proceedings of the IEEE International Conference on Sensor Networks, 2008

A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms.
Proceedings of the Principles of Distributed Systems, 12th International Conference, 2008

2007
Power-Aware Real-Time Scheduling upon Identical Multiprocessor Platforms
CoRR, 2007

A Framework Introducing Model Reversibility in SoC Design Space Exploration.
Proceedings of the Embedded Computer Systems: Architectures, 2007

2005
Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005


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