Rohit Sinha

Orcid: 0000-0001-9107-0239

Affiliations:
  • Visa Research
  • University of California at Berkeley, CA, USA


According to our database1, Rohit Sinha authored at least 27 papers between 2011 and 2024.

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Timeline

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Bibliography

2024
HiSE: Hierarchical (Threshold) Symmetric-key Encryption.
IACR Cryptol. ePrint Arch., 2024

2023
hinTS: Threshold Signatures with Silent Setup.
IACR Cryptol. ePrint Arch., 2023

How to Design Fair Protocols in the Multi-Blockchain Setting.
IACR Cryptol. ePrint Arch., 2023

SublonK: Sublinear Prover PlonK.
IACR Cryptol. ePrint Arch., 2023

Threshold Signatures in the Multiverse.
IACR Cryptol. ePrint Arch., 2023

LucidiTEE: Scalable Policy-Based Multiparty Computation with Fairness.
Proceedings of the Cryptology and Network Security - 22nd International Conference, 2023

2022
Cryptography with Weights: MPC, Encryption and Signatures.
IACR Cryptol. ePrint Arch., 2022

i-TiRE: Incremental Timed-Release Encryption or How to use Timed-Release Encryption on Blockchains?
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022

2021
Reducing HSM Reliance in Payments through Proxy Re-Encryption.
IACR Cryptol. ePrint Arch., 2021

Amortized Threshold Symmetric-key Encryption.
IACR Cryptol. ePrint Arch., 2021

TEMP: Time-locked Encryption Made Practical.
IACR Cryptol. ePrint Arch., 2021

2020
Verification of Quantitative Hyperproperties Using Trace Enumeration Relations.
Proceedings of the Computer Aided Verification - 32nd International Conference, 2020

2019
LucidiTEE: Policy-based Fair Computing at Scale.
IACR Cryptol. ePrint Arch., 2019

2018
VeritasDB: High Throughput Key-Value Store with Integrity.
IACR Cryptol. ePrint Arch., 2018

2017
Secure Computing using Certified Software and Trusted Hardware.
PhD thesis, 2017

A Formal Foundation for Secure Remote Execution of Enclaves.
IACR Cryptol. ePrint Arch., 2017

A compiler and verifier for page access oblivious computation.
Proceedings of the 2017 11th Joint Meeting on Foundations of Software Engineering, 2017

2016
A design and verification methodology for secure isolated regions.
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2016

2015
Moat: Verifying Confidentiality of Enclave Programs.
Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security, 2015

Automatic Rootcausing for Program Equivalence Failures in Binaries.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014
Formal Modeling and Verification of CloudProxy.
Proceedings of the Verified Software: Theories, Tools and Experiments, 2014

2013
Symbolic software model validation.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2012
synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Verification with small and short worlds.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Abstract state machines as an intermediate representation for high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011


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