Pramod Subramanyan

Orcid: 0000-0003-2288-3396

According to our database1, Pramod Subramanyan authored at least 33 papers between 2010 and 2023.

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Bibliography

2023
Analysis of Linux-PRNG (Pseudo Random Number Generator).
CoRR, 2023

2021
PSec: Programming Secure Distributed Systems using Enclaves.
Proceedings of the ASIA CCS '21: ACM Asia Conference on Computer and Communications Security, 2021

2020
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks.
ACM Trans. Design Autom. Electr. Syst., 2020

Functional Analysis Attacks on Logic Locking.
IEEE Trans. Inf. Forensics Secur., 2020

When Oblivious is Not: Attacks against OPAM.
Proceedings of the 14th USENIX Workshop on Offensive Technologies, 2020

Mining Hyperproperties from Behavioral Traces.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

HyperFuzzing for SoC Security Validation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Verification of Quantitative Hyperproperties Using Trace Enumeration Relations.
Proceedings of the Computer Aided Verification - 32nd International Conference, 2020

2019
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification.
ACM Trans. Design Autom. Electr. Syst., 2019

Verification of Authenticated Firmware Load.
IACR Cryptol. ePrint Arch., 2019

A Formal Approach to Secure Speculation.
IACR Cryptol. ePrint Arch., 2019

Verification of Authenticated Firmware Loaders.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

Towards Verifiably Secure Systems-on-Chip Platforms.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

UCLID5: Integrating Modeling, Verification, Synthesis and Learning.
Proceedings of the 16th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2018

Lazy Self-composition for Security Verification.
Proceedings of the Computer Aided Verification - 30th International Conference, 2018

2017
A Formal Foundation for Secure Remote Execution of Enclaves.
IACR Cryptol. ePrint Arch., 2017

Malware detection using machine learning based analysis of virtual memory access patterns.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Verifying information flow properties of firmware using symbolic execution.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Specification and modeling for systems-on-chip security verification.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Evaluating the security of logic encryption algorithms.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Template-based Synthesis of Instruction-Level Abstractions for SoC Verification.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

2014
Boolean Satisfiability: Solvers and Extensions.
Proceedings of the Software Systems Safety, 2014

Reverse Engineering Digital Circuits Using Structural and Functional Analyses.
IEEE Trans. Emerg. Top. Comput., 2014

All-SAT Using Minimal Blocking Clauses.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Template-based circuit understanding.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

Formal verification of taint-propagation security properties in a commercial SoC design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
WordRev: Finding word-level structures in a sea of bit-level gates.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Reverse engineering digital circuits using functional analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Energy-efficient redundant execution for chip multiprocessors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors.
Proceedings of the Design, Automation and Test in Europe, 2010


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