Ronny Krashinsky

According to our database1, Ronny Krashinsky authored at least 14 papers between 2001 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Pretraining Large Language Models with NVFP4.
CoRR, September, 2025

2024
Reducing the Cost of Dropout in Flash-Attention by Hiding RNG with GEMM.
CoRR, 2024

2021
NVIDIA A100 Tensor Core GPU: Performance and Innovation.
IEEE Micro, 2021

3.2 The A100 Datacenter GPU and Ampere Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2014
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Convergence and scalarization for data-parallel architectures.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2008
Implementing the scale vector-thread processor.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
Vector-thread architecture and implementation.
PhD thesis, 2007

2004
Cache Refill/Access Decoupling for Vector Machines.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

The Vector-Thread Architecture.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2002
Minimizing energy for wireless web access with bounded slowdown.
Proceedings of the Eighth Annual International Conference on Mobile Computing and Networking, 2002

2001
Multithreading decoupled architectures for complexity-effective general purpose computing.
SIGARCH Comput. Archit. News, 2001

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001


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