Rudolf Ritter

According to our database1, Rudolf Ritter authored at least 17 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection.
IEEE J. Solid State Circuits, 2016

Using www.sigma-delta.de to rapidly obtain ELD compensated CT ΣΔ modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Finite GBW in single OpAmp CT ΣΔ modulators.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Phase noise vs. jitter analysis in continuous-time LP and BP ΣΔ modulators with interferers.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Estimation of Non-Idealities in Sigma-Delta Modulators for Test and Correction Using Unscented Kalman Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Continuous-Time Delta-Sigma ADCs With Improved Interferer Rejection.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Anti-aliasing filter improvement in continuous-time feedback sigma-delta modulators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A Genetic Algorithm for the Estimation of Nonidealities in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A high open loop gain common mode feedback technique for fully differential amplifiers.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A square root unscented Kalman filter for estimating DAC and loopfilter nonidealities in continuous-time sigma-delta modulators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Design of a high linearity Gm stage for a high speed current mode SAR ADC.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Integrator swing reduction in feedback compensated Sigma-Delta modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Concurrent estimation of amplifier nonidealities and excess loop delay in continuous-time sigma-delta modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low power quantizer design in CT Delta Sigma modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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