John G. Kauffman

According to our database1, John G. Kauffman authored at least 22 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Minimizing Signal-Dependent Residue in CT Pipelined ADCs.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

FIR Filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
FIR DACs in CT Incremental Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
A Multi-mode GSM to LTE100 ADC.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2016
A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection.
IEEE J. Solid State Circuits, 2016

2014
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW.
IEEE J. Solid State Circuits, 2014

A 1.92-GS/s CT ΔΣ modulator with 70-db DR and 78-db SFDR in 15-MHz bandwidth.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013
Integrator swing reduction in feedback compensated Sigma-Delta modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low power quantizer design in CT Delta Sigma modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Analysis and design of high speed/high linearity continuous time delta-sigma modulator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
PVT robust design of wideband CT delta sigma modulators including finite GBW compensation.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A reconfigurable Continuous-Time ΔΣ-ADC using a digitally programmable gm-C array.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR.
IEEE J. Solid State Circuits, 2011

An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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