John G. Kauffman
Orcid: 0000-0003-3840-6885
According to our database1,
John G. Kauffman
authored at least 34 papers
between 2011 and 2023.
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Bibliography
2023
Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop.
IEEE Trans. Biomed. Circuits Syst., 2022
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
A Comparative Study of Noise Behavior in Single-Opamp Resonators in Delta-Sigma Modulators.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2018
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2016
A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection.
IEEE J. Solid State Circuits, 2016
2014
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW.
IEEE J. Solid State Circuits, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Analysis and design of high speed/high linearity continuous time delta-sigma modulator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
PVT robust design of wideband CT delta sigma modulators including finite GBW compensation.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR.
IEEE J. Solid State Circuits, 2011
An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011