Joachim Becker
Orcid: 0000-0002-2125-7812
According to our database1,
Joachim Becker
authored at least 73 papers
between 1998 and 2023.
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Bibliography
2023
NeuroBus - Architecture and Communication Bus for an Ultra-Flexible Neural Interface.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Assessing Flexibility of Organizations for Strategic Development of Agricultural Business Projects.
Proceedings of the 7th International Conference on Computational Linguistics and Intelligent Systems. Volume I: Machine Learning Workshop, 2023
2022
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
PUF-Entropy Extraction of DAC Intersymbol-Interference using Continuous-Time Delta-Sigma ADCs.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Erratum to "A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System-on-Chip".
IEEE J. Solid State Circuits, 2021
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip.
IEEE J. Solid State Circuits, 2021
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Normalization and Multi-Valued Symbol Extraction From RO-PUFs for Enhanced Uniform Probability Distributions.
IEEE Trans. Circuits Syst., 2020
Comparison of Measurement and Readout Strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Live Demonstration: Generating FPGA Fingerprints Utilizing Full-Chip Characterization with Ring-Oscillator PUFs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
2018
A 0.4-V G<sub>m</sub>-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR.
IEEE J. Solid State Circuits, 2018
A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s.
IEEE J. Solid State Circuits, 2018
Comparison Study of Integrated Potentiostats: Resistive-TIA, Capacitive-TIA, CT ΣΔ Modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Evaluation of spike sorting and compression for digitally reconfigurable non-uniform quantization.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Evaluation of single-bit sigma-delta modulator DAC for electrical impedance spectroscopy.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Exploiting Weak PUFs From Data Converter Nonlinearity - E.g., A Multibit CT ΔΣ Modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
An array of fully-integrated quadrature TX/RX NMR field probes for MRI trajectory mapping.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Finite GBW compensation technique for CT ΔΣ modulators with differentiator based ELD compensation.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
2014
A Genetic Algorithm for the Estimation of Nonidealities in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW.
IEEE J. Solid State Circuits, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance.
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Live demonstration: In vivo verification of a 100 Mbps transcutaneous optical telemetric link.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
A multi-channel neural stimulator with resonance compensated inductive receiver and closed-loop smart power management.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Analysis and design of high speed/high linearity continuous time delta-sigma modulator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Hardware-Accelerated Simulation Environment for CT Sigma-Delta Modulators Using an FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants.
IEEE J. Solid State Circuits, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Digitally-switched resonators for bandpass integrated transmission line ΣΔ modulators.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A multichannel neurostimulator with transcutaneous closed-loop power control and self-adaptive supply.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Distributed clock gating for power reduction of a programmable waveform generator for neural stimulation.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
2011
A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR.
IEEE J. Solid State Circuits, 2011
A neural stimulator front-end with arbitrary pulse shape, HV compliance and adaptive supply requiring 0.05mm<sup>2</sup> in 0.35μm HVCMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
An AC-powered optical receiver consuming 270μW for transcutaneous 2Mb/s data transfer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
A Field-Programmable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal Lattice.
IEEE J. Solid State Circuits, 2008
A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBW.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A rapid prototyping environment for high-speed reconfigurable analog signal processing.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
A GP algorithm for efficient synthesis of GM-C filters on a hexagonal FPAA structure.
Proceedings of the Genetic and Evolutionary Computation Conference, 2008
2007
A Unified Environment for Design Entry and 3D Animation of Analog Circuits Schematics.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C Filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm.
Proceedings of the Genetic and Evolutionary Computation Conference, 2007
A field programmable Gm-C filter array (FPAA) for online adaptation to environmental changes.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2005
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
2004
A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable G<sub>M</sub>-cells.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
2001
Proceedings of the Evolvable Systems: From Biology to Hardware, 2001
Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001
1998
Proceedings of the Visualization in Scientific Computing '98, 1998