Rudy Beraha

According to our database, Rudy Beraha authored at least 6 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2018

A 9-mm² Ultra-Low-Power Highly Integrated 28-nm CMOS SoC for Internet of Things.

Yu Pu, Chunlei Shi, Giby Samson, Dongkyu Park, Ken Easton, Rudy Beraha, Adam Newham, Mark Lin, Venkat Rangan, Karam Chatha, Danny Butterfield, Rashid Attar

IEEE J. Solid State Circuits, 2018

2017

Blackghost: An ultra-low-power all-in-one 28nm CMOS SoC for Internet-of-Things.

Yu Pu, Giby Samson, Chunlei Shi, Dongkyu Park, Ken Easton, Rudy Beraha, J. Hadi, Mark Lin, E. Arvelo, J. Fatehi, J. Kumar, Moses Derkalousdian, P. Aghera, Adam Newham, H. Sheraji, Karam Chatha, R. McLaren, V. Ganesan, S. Namasivayam, Danny Butterfield, Ravi Shenoy, Rashid Attar

Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2014

Minimizing clock domain crossing in Network on Chip interconnect.

Parag Kulkarni, Puneet Gupta, Rudy Beraha

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2011

Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study.

Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study.

Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Design, Automation and Test in Europe, 2010

2009

The design of a latency constrained, power optimized NoC for a 4G SoC.

Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Third International Symposium on Networks-on-Chips, 2009