Ruihua Yu
Orcid: 0009-0003-7040-6719
According to our database1,
Ruihua Yu authored at least 5 papers
between 2023 and 2026.
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Bibliography
2026
MiniBuf: An On-Chip Buffer Allocation Framework Toward Minimizing Buffer Size and Latency for Memristor-Based CNN Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026
2024
Core patent forecasting based on graph neural networks with an application in stock markets.
Technol. Anal. Strateg. Manag., August, 2024
2023
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci., December, 2023
A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the International Conference on IC Design and Technology, 2023