Hu He
Orcid: 0000-0003-3239-430XAffiliations:
- Tsinghua University, School of Integrated Circuits, Beijing Innovation Center for Future Chips (ICFC), China
- Tsinghua University, Institute of Microelectronics, Beijing, China (PhD 2004)
According to our database1,
Hu He
authored at least 31 papers
between 2005 and 2023.
Collaborative distances:
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Bibliography
2023
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci., December, 2023
A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
Proceedings of the ICMSSP 2020: 5th International Conference on Multimedia Systems and Signal Processing, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things.
Sensors, 2019
A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications.
Sensors, 2019
J. Circuits Syst. Comput., 2019
Exploration of a mechanism to form bionic, self-growing and self-organizing neural network.
Artif. Intell. Rev., 2019
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
2017
On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage.
Comput. J., 2017
2016
VLSI Design, 2016
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
An Implementation of Message-Passing Interface over VxWorks for Real-Time Embedded Multi-Core Systems.
Comput. J., 2014
2013
Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems.
IET Wirel. Sens. Syst., 2013
2012
Sensors, 2012
2011
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.
J. Electron. Test., 2011
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.
J. Electron. Test., 2011
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
2009
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures.
J. Low Power Electron., 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
J. Low Power Electron., 2007
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006
2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005