He Qian
Orcid: 0000-0003-3377-5366
According to our database1,
He Qian
authored at least 54 papers
between 2005 and 2023.
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Bibliography
2023
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci., December, 2023
Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips.
Sci. China Inf. Sci., October, 2023
A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Uncertainty quantification via a memristor Bayesian deep neural network for risk-sensitive reinforcement learning.
Nat. Mac. Intell., July, 2023
BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
An RRAM retention prediction framework using a convolutional neural network based on relaxation behavior.
Neuromorph. Comput. Eng., March, 2023
Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
2022
Large-Scale Integrated Flexible Tactile Sensor Array for Sensitive Smart Robotic Touch.
CoRR, 2022
A Physical Reservoir Computing Model Based on Volatile Memristor for Temporal Signal Processing.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proc. IEEE, 2021
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.
IEEE J. Solid State Circuits, 2021
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.
CoRR, 2021
Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips.
Sci. China Inf. Sci., 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Impact of Bottom Electrode Roughness on the Analog Switching Characteristics in Nanoscale RRAM Array.
Proceedings of the Device Research Conference, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A circuit-algorithm codesign method to reduce the accuracy drop of RRAM based computing-in-memory chip.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
HABEm: Hierarchical Attribute Based Encryption with Multi-Authority for the Mobile Cloud Service.
Proceedings of the 9th IEEE/CIC International Conference on Communications in China, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10<sup>-6</sup> Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Sign backpropagation: An on-chip learning algorithm for analog RRAM neuromorphic computing systems.
Neural Networks, 2018
Proceedings of the 13th IEEE Annual International Conference on Nano/Micro Engineered and Molecular Systems, 2018
2017
Proc. IEEE, 2017
New structure with SiO<sub>2</sub>-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memory.
Microelectron. Reliab., 2017
Sci. China Inf. Sci., 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
1S1R device with self-compliance property for high density cross-point memory applications.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
2014
Geometric projection-based switching policy for multiple energy harvesting transmitters.
CoRR, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm<sup>2</sup> Die Size in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm<sup>2</sup> Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Understanding dynamic behavior of mm-wave CML divider with injection-locking concept.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2006
Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006
2005
Growth and characterization of 0.8-µm gate length AlGaN/GaN HEMTs on sapphire substrates.
Sci. China Ser. F Inf. Sci., 2005