Dong Wu

According to our database1, Dong Wu authored at least 51 papers between 2003 and 2019.

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Bibliography

2019
L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks.
IEEE Trans. Neural Netw. Learning Syst., 2019

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Memory Trojan Attack on Neural Network Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Localization Performance of Multiple Vibrotactile Cues on Both Arms.
IEEE Trans. Haptics, 2018

A new medical diagnosis method based on Z-numbers.
Appl. Intell., 2018

R2D2: Runtime reassurance and detection of A2 Trojan.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Improved Phonotactic Language Recognition Using Collaborated Language Model.
Proceedings of the 5th IEEE International Conference on Cloud Computing and Intelligence Systems, 2018

Interaction Technology Based on 3D printing topographic sand table for Emergency Management.
Proceedings of the 2018 2nd International Conference on Big Data and Internet of Things, 2018

2017
Motion-based skin region of interest detection with a real-time connected component labeling algorithm.
Multimedia Tools Appl., 2017

Parameter-less Auto-weighted multiple graph regularized Nonnegative Matrix Factorization for data representation.
Knowl.-Based Syst., 2017

Multiple Laplacian graph regularised low-rank representation with application to image representation.
IET Image Processing, 2017

Ultrasonic image reconstruction based on maximum likelihood expectation maximization for concrete structural information.
Computers & Electrical Engineering, 2017

Long Short-Term Memory With Quadratic Connections in Recursive Neural Networks for Representing Compositional Semantics.
IEEE Access, 2017

Hierarchical Parameter Sharing in Recursive Neural Networks with Long Short-Term Memory.
Proceedings of the Neural Information Processing - 24th International Conference, 2017

Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Image Sharpness Assessment by Sparse Representation.
IEEE Trans. Multimedia, 2016

No-reference Image Quality Assessment With A Gradient-induced Dictionary.
TIIS, 2016

2015
A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays.
IEEE Trans. on Circuits and Systems, 2015

A Further Finite Element Stress Analysis of Angled Abutments for an Implant Placed in the Anterior Maxilla.
Comp. Math. Methods in Medicine, 2015

A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time.
SCIENCE CHINA Information Sciences, 2015

A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 16 Mb RRAM test chip based on analog power system with tunable write pulses.
Proceedings of the 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

Effect of vibrotactile cues for guiding simultaneous procedural motion of two joints on upper limbs.
Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

A real-time interactive data mining and visualization system using parallel computing.
Proceedings of the Tenth International Conference on Digital Information Management, 2015

Performance of simultaneous motion and respiration control under guidance of audio-haptic cues.
Proceedings of the 2015 IEEE World Haptics Conference, 2015

Integrating Opinion Leader and User Preference for Recommendation.
Proceedings of the Database Systems for Advanced Applications, 2015

Air-gap/SiO2 liner TSVs with improved electrical performance.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
IEEE Trans. VLSI Syst., 2014

Image quality assessment based on multi-scale representation of structure.
Digital Signal Processing, 2014

Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology.
SCIENCE CHINA Information Sciences, 2014

An ultra-low-power extended counting ADC For large scale sensor arrays.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Using C to implement high-efficient computation of dense optical flow on FPGA-accelerated heterogeneous platforms.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
User acceptance of software as a service: Evidence from customers of China's leading e-commerce company, Alibaba.
Journal of Systems and Software, 2013

Combinatorial Aspects of Mixed Arrangements.
Ars Comb., 2013

A 15-bit two-step sigma-delta ADC with embedded compression for image sensor array.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Parallelizing sparse LU decomposition on FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.
J. Electronic Testing, 2011

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.
J. Electronic Testing, 2011

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Evolution of supercomputers.
Frontiers Comput. Sci. China, 2010

A novel high-speed and low-power negative voltage level shifter for low voltage applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 13-bit, low-power, compact ADC suitable for sensor applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories.
IEEE Trans. on Circuits and Systems, 2009

Embedded high-speed BCH decoder for new-generation NOR flash memories.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Deriving Marine-Boundary-Layer Lapse Rate from Collocated CALIPSO, MODIS, and AMSR-E Data to Study Global Low-Cloud Height Statistics.
IEEE Geosci. Remote Sensing Lett., 2008

Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Improving routing efficiency for network-on-chip through contention-aware input selection.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Investigation into energy-efficient co-synthesis of distributed embedded systems.
PhD thesis, 2004

2003
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.
Proceedings of the 2003 Design, 2003


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