Bin Gao

Orcid: 0000-0002-2417-983X

Affiliations:
  • Tsinghua University, Institute of Microelectronics, Beijing, China
  • Peking University, Institute of Microelectronics, Beijing, China (PhD 2013)


According to our database1, Bin Gao authored at least 53 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci., December, 2023

Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips.
Sci. China Inf. Sci., October, 2023

A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Uncertainty quantification via a memristor Bayesian deep neural network for risk-sensitive reinforcement learning.
Nat. Mac. Intell., July, 2023

BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

An RRAM retention prediction framework using a convolutional neural network based on relaxation behavior.
Neuromorph. Comput. Eng., March, 2023

Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Thermal Induced Retention Degradation of RRAM-based Neuromorphic Computing Chips.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Impact of Programming Process on Temperature Coefficient in Analog RRAM.
Proceedings of the International Conference on IC Design and Technology, 2023

Memristor Based Mixed-Accuracy Computation-in-Memory System.
Proceedings of the International Conference on IC Design and Technology, 2023

Memristor Based Mixed-Precision Computation-in-Memory System.
Proceedings of the International Conference on IC Design and Technology, 2023

2022
Complementary Memtransistor-Based Multilayer Neural Networks for Online Supervised Learning Through (Anti-)Spike-Timing-Dependent Plasticity.
IEEE Trans. Neural Networks Learn. Syst., 2022

A compute-in-memory chip based on resistive random-access memory.
Nat., 2022

Large-Scale Integrated Flexible Tactile Sensor Array for Sensitive Smart Robotic Touch.
CoRR, 2022

A Physical Reservoir Computing Model Based on Volatile Memristor for Temporal Signal Processing.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

In-memory Learning with Analog Resistive Switching Memory: A Review and Perspective.
Proc. IEEE, 2021

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.
IEEE J. Solid State Circuits, 2021

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.
CoRR, 2021

Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips.
Sci. China Inf. Sci., 2021

Recent progress of integrated circuits and optoelectronic chips.
Sci. China Inf. Sci., 2021

HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

System and Technology Co-optimization for RRAM based Computation-in-memory Chip.
Proceedings of the International Conference on IC Design and Technology, 2021

Impact of Bottom Electrode Roughness on the Analog Switching Characteristics in Nanoscale RRAM Array.
Proceedings of the Device Research Conference, 2021

An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A circuit-algorithm codesign method to reduce the accuracy drop of RRAM based computing-in-memory chip.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
Three-Dimensional nand Flash for Vector-Matrix Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Parallelizable Algorithms for Optimization Problems with Orthogonality Constraints.
SIAM J. Sci. Comput., 2019

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10<sup>-6</sup> Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Reliability Perspective on Neuromorphic Computing Based on Analog RRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A New First-Order Algorithmic Framework for Optimization Problems with Orthogonality Constraints.
SIAM J. Optim., 2018

Sign backpropagation: An on-chip learning algorithm for analog RRAM neuromorphic computing systems.
Neural Networks, 2018

2017
Resistive Random Access Memory for Future Information Processing System.
Proc. IEEE, 2017

New structure with SiO<sub>2</sub>-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memory.
Microelectron. Reliab., 2017

Neuromorphic Computing based on Resistive RAM.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays.
CoRR, 2016

Physical understanding and optimization of resistive switching characteristics in oxide-RRAM.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

RRAM Cross-Point Arrays.
Proceedings of the 3D Flash Memories, 2016

2015
The effect of variation on neuromorphic network based on 1T1R memristor array.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

RRAM based synaptic devices for neuromorphic visual systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Modeling and design optimization of ReRAM.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Design guidelines for 3D RRAM cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Parameters extraction on HfOX based RRAM.
Proceedings of the 44th European Solid State Device Research Conference, 2014


  Loading...