Huaqiang Wu

Orcid: 0000-0001-8359-7997

According to our database1, Huaqiang Wu authored at least 60 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Scaling Limits of Memristor-Based Routers for Asynchronous Neuromorphic Systems.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

3.2 A 0.028mm² 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from -40°C to 125°C and ±1600ppm Inaccuracy After Accelerated Aging.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.
Sci. China Inf. Sci., December, 2023

Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips.
Sci. China Inf. Sci., October, 2023

A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Uncertainty quantification via a memristor Bayesian deep neural network for risk-sensitive reinforcement learning.
Nat. Mac. Intell., July, 2023

BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

An RRAM retention prediction framework using a convolutional neural network based on relaxation behavior.
Neuromorph. Comput. Eng., March, 2023

Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Thermal Induced Retention Degradation of RRAM-based Neuromorphic Computing Chips.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Impact of Programming Process on Temperature Coefficient in Analog RRAM.
Proceedings of the International Conference on IC Design and Technology, 2023

A 7.4μJ.ppm2 Resistance Sensor with ±120ppm (3σ) 1-Point-Trimmed Inaccuracy and <4ppm/°C Temperature Drift from -55°C to 125°C.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
2022 roadmap on neuromorphic devices and applications research in China.
Neuromorph. Comput. Eng., December, 2022

A compute-in-memory chip based on resistive random-access memory.
Nat., 2022

Large-Scale Integrated Flexible Tactile Sensor Array for Sensitive Smart Robotic Touch.
CoRR, 2022

Improving the accuracy of neural networks in analog computing-in-memory systems by analog weight.
Proceedings of the 26th International Conference on Pattern Recognition, 2022

A Physical Reservoir Computing Model Based on Volatile Memristor for Temporal Signal Processing.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

In-memory Learning with Analog Resistive Switching Memory: A Review and Perspective.
Proc. IEEE, 2021

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.
IEEE J. Solid State Circuits, 2021

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.
CoRR, 2021

Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips.
Sci. China Inf. Sci., 2021

Recent progress of integrated circuits and optoelectronic chips.
Sci. China Inf. Sci., 2021

HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Impact of Bottom Electrode Roughness on the Analog Switching Characteristics in Nanoscale RRAM Array.
Proceedings of the Device Research Conference, 2021

An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Large-scale neuromorphic optoelectronic computing with a reconfigurable diffractive processing unit.
CoRR, 2020

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Three-Dimensional nand Flash for Vector-Matrix Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2019

On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

In situ training of feed-forward and recurrent convolutional memristor networks.
Nat. Mach. Intell., 2019

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10<sup>-6</sup> Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Reliability Perspective on Neuromorphic Computing Based on Analog RRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Sign backpropagation: An on-chip learning algorithm for analog RRAM neuromorphic computing systems.
Neural Networks, 2018

Building Towards "Invisible Cloak": Robust Physical Adversarial Attack on YOLO Object Detector.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

A Novel Graphene Double-Balanced Passive Mixer.
Proceedings of the 13th IEEE Annual International Conference on Nano/Micro Engineered and Molecular Systems, 2018

R2D2: Runtime reassurance and detection of A2 Trojan.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
Resistive Random Access Memory for Future Information Processing System.
Proc. IEEE, 2017

New structure with SiO<sub>2</sub>-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memory.
Microelectron. Reliab., 2017

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Neuromorphic Computing based on Resistive RAM.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

RRAM Cross-Point Arrays.
Proceedings of the 3D Flash Memories, 2016

2015
The effect of variation on neuromorphic network based on 1T1R memristor array.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Theory study and implementation of configurable ECC on RRAM memory.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

A 16 Mb RRAM test chip based on analog power system with tunable write pulses.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Synaptic learning behaviors achieved by metal ion migration in a Cu/PEDOT: PSS/Ta memristor.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

1S1R device with self-compliance property for high density cross-point memory applications.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Graphene oxide and TiO2 nano-particle composite based nonvolatile memory.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

2014
Stack engineering for ReRAM devices performance improvement.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014


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