Russell Schreiber

According to our database, Russell Schreiber authored at least 8 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core.

Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.

John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Zen3: The AMD 2^nd-Generation 7nm x86-64 Microprocessor Core.

Thomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020

2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core.

Teja Singh, Sundar Rangarajan, Deepesh John, Russell Schreiber, Spence Oliver, Rajit Seahra, Alex Schaefer

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

Zen: An Energy-Efficient High-Performance × 86 Core.

Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak

IEEE J. Solid State Circuits, 2018

2016

Carrizo: A High Performance, Energy Efficient 28 nm APU.

Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox

IEEE J. Solid State Circuits, 2016

2015

4.8 A 28nm x86 APU optimized for power and area efficiency.

Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011

An 8MB level-3 cache in 32nm SOI with column-select aliasing.

Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu

Proceedings of the IEEE International Solid-State Circuits Conference, 2011