Don Weiss

According to our database, Don Weiss authored at least 5 papers between 1994 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

An 8MB level-3 cache in 32nm SOI with column-select aliasing.

Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology.

Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2002

The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor.

Don Weiss, John J. Wuu, Victor Chin

IEEE J. Solid State Circuits, 2002

1996

PA7300LC Integrates Cache for Cost/Performance.

Dave Hollenbeck, Steven R. Undy, Leith Johnson, Don Weiss, Paul Tobin, Richard Carlson

Proceedings of the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, 1996

1994

A Workstation I/O System on a Chip.

Tom Spencer, Frank Lettang, Curtis McAllister, Tony Riccio, Joe Orth, Don Weiss, Brian Arnold

Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994