Hugh McIntyre

According to our database, Hugh McIntyre authored at least 8 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems.

Alan Smith, Eric Chapman, Chintan Patel, Raja Swaminathan, John J. Wuu, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2017

3.2 Zen: A next-generation high-performance ×86 core.

Teja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Carrizo: A High Performance, Energy Efficient 28 nm APU.

Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox

IEEE J. Solid State Circuits, 2016

2015

4.8 A 28nm x86 APU optimized for power and area efficiency.

Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012

Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS.

Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh

IEEE J. Solid State Circuits, 2012

2011

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.

Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2005

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor.

Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena

IEEE J. Solid State Circuits, 2005

2000

A third-generation SPARC V9 64-b microprocessor.

Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You

IEEE J. Solid State Circuits, 2000