S. V. Dilip Kumar

Orcid: 0000-0003-0057-1658

According to our database1, S. V. Dilip Kumar authored at least 8 papers between 2016 and 2025.

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Bibliography

2025
Higher-Order Time Sharing Masking.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025

2024
Time Sharing - A Novel Approach to Low-Latency Masking.
IACR Cryptol. ePrint Arch., 2024

2023
Uncovering Vulnerabilities in Smartphone Cryptography: A Timing Analysis of the Bouncy Castle RSA Implementation.
IACR Cryptol. ePrint Arch., 2023

Low-Cost First-Order Secure Boolean Masking in Glitchy Hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2018
An In-Depth and Black-Box Characterization of the Effects of Laser Pulses on ATmega328P.
Proceedings of the Smart Card Research and Advanced Applications, 2018

2017
Two Efficient Fault-Based Attacks on CLOC and SILC.
J. Hardw. Syst. Secur., 2017

A Practical Fault Attack on ARX-Like Ciphers with a Case Study on ChaCha20.
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017

2016
Fault Based Almost Universal Forgeries on CLOC and SILC.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016


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