Sarani Bhattacharya

Orcid: 0000-0002-4190-2671

According to our database1, Sarani Bhattacharya authored at least 37 papers between 2012 and 2023.

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Bibliography

2023
"Whispering MLaaS" Exploiting Timing Channels to Compromise User Privacy in Deep Neural Networks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

A practical key-recovery attack on LWE-based key- encapsulation mechanism schemes using Rowhammer.
IACR Cryptol. ePrint Arch., 2023

Uncovering Vulnerabilities in Smartphone Cryptography: A Timing Analysis of the Bouncy Castle RSA Implementation.
IACR Cryptol. ePrint Arch., 2023

On the Amplification of Cache Occupancy Attacks in Randomized Cache Architectures.
CoRR, 2023

A short note on the paper 'Are Randomized Caches Really Random?'.
CoRR, 2023

Are Randomized Caches Truly Random? Formal Analysis of Randomized-Partitioned Caches.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
On the Evaluation of User Privacy in Deep Neural Networks using Timing Side Channel.
CoRR, 2022

Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Breaking KASLR on Mobile Devices without Any Use of Cache Memory.
Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022

2021
RASSLE: Return Address Stack based Side-channel LEakage.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Victims Can Be Saviors: A Machine Learning-based Detection for Micro-Architectural Side-Channel Attacks.
ACM J. Emerg. Technol. Comput. Syst., 2021

Exploring Micro-architectural Side-Channel Leakages through Statistical Testing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Branch Prediction Attack on Blinded Scalar Multiplication.
IEEE Trans. Computers, 2020

Rowhammer Induced Intermittent Fault Attack on ECC-hardened memory.
IACR Cryptol. ePrint Arch., 2020

RAPPER: Ransomware Prevention via Performance Counters.
CoRR, 2020

ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block Ciphers.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
IPA: an Instruction Profiling-Based Micro-architectural Side-Channel Attack on Block Ciphers.
J. Hardw. Syst. Secur., 2019

Using Memory Allocation Schemes in Linux to Exploit DRAM Vulnerability: with Rowhammer as a Case Study.
CoRR, 2019

RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

In-situ Extraction of Randomness from Computer Architecture Through Hardware Performance Counters.
Proceedings of the Smart Card Research and Advanced Applications, 2019

2018
Utilizing Performance Counters for Compromising Public Key Ciphers.
ACM Trans. Priv. Secur., 2018

Customized Instructions for Protection Against Memory Integrity Attacks.
IEEE Embed. Syst. Lett., 2018

RAPPER: Ransomware Prevention via Performance Counters.
CoRR, 2018

Online Detection and Reactive Countermeasure for Leakage from BPU Using TVLA.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Rapid detection of rowhammer attacks using dynamic skewed hash tree.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

2017
Formal fault analysis of branch predictors: attacking countermeasures of asymmetric key ciphers.
J. Cryptogr. Eng., 2017

Template Attack on Blinded Scalar Multiplication with Asynchronous perf-ioctl Calls.
IACR Cryptol. ePrint Arch., 2017

Performance Counters to Rescue: A Machine Learning based safeguard against Micro-architectural Side-Channel-Attacks.
IACR Cryptol. ePrint Arch., 2017

Tackling the Time-Defence: An Instruction Count Based Micro-architectural Side-Channel Attack on Block Ciphers.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2017

2016
Template attack on SPA and FA resistant implementation of Montgomery ladder.
IET Inf. Secur., 2016

Curious case of Rowhammer: Flipping Secret Exponent Bits using Timing Analysis.
IACR Cryptol. ePrint Arch., 2016

SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

2015
Who watches the watchmen? : Utilizing Performance Monitors for Compromising keys of RSA on Intel Platforms.
IACR Cryptol. ePrint Arch., 2015

2014
Fault Attack revealing Secret Keys of Exponentiation Algorithms from Branch Prediction Misses.
IACR Cryptol. ePrint Arch., 2014

2013
Unraveling timewarp: what all the fuzz is about?
Proceedings of the HASP 2013, 2013

2012
Hardware Prefetchers Leak: A Revisit of SVF for Cache-Timing Attacks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012


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