Saied Hemati

According to our database1, Saied Hemati authored at least 36 papers between 2003 and 2020.

Collaborative distances:



In proceedings 
PhD thesis 




Personality Assessment from Text for Machine Commonsense Reasoning.
CoRR, 2020

Human-in-the-loop Learning for Personalized Diet Monitoring from Unstructured Mobile Data.
ACM Trans. Interact. Intell. Syst., 2019

Symbol-Level Stochastic Chase Decoding of Reed-Solomon and BCH Codes.
IEEE Trans. Commun., 2019

A Modular Architecture for Structured Long Block-Length LDPC Decoders.
J. Signal Process. Syst., 2018

Dynamics of ML Approaching Randomized Decoders on Graphs with Cycles.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Power Grid Resiliency Improvement Through Remedial Action Schemes.
Proceedings of the IECON 2018, 2018

Symbolic Stochastic Chase Decoding of Reed-Solomon and BCH Codes.
CoRR, 2017

A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes.
IEEE Commun. Lett., 2016

Mitigating hardware cyber-security risks in error correcting decoders.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Exploiting dental implants for creating wired implantable health monitoring devices.
Proceedings of the 18th IEEE International Conference on e-Health Networking, 2016

Efficient implementation of structured long block-length LDPC codes.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing.
IEEE Trans. Signal Process., 2014

Energy-efficient gear-shift LDPC decoders.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes.
IEEE Trans. Signal Process., 2013

Stochastic Decoding of LDPC Codes over GF(q).
IEEE Trans. Commun., 2013

Relaxed Half-Stochastic Belief Propagation.
IEEE Trans. Commun., 2013

Dithered Belief Propagation Decoding.
IEEE Trans. Commun., 2012

Low-Complexity Channel-Likelihood Estimation for Non-Binary Codes and QAM.
IEEE Commun. Lett., 2012

Stochastic chase decoder for reed-solomon codes.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Majority-based tracking forecast memories for stochastic LDPC decoding.
IEEE Trans. Signal Process., 2010

On the Dynamics of Analog Min-Sum Iterative Decoders: An Analytical Approach.
IEEE Trans. Commun., 2010

Dynamics of analog decoders for different message representation domains.
IEEE Trans. Commun., 2010

A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Stochastic Chase Decoding of Reed-Solomon Codes.
IEEE Commun. Lett., 2010

Lowering Error Floors Using Dithered Belief Propagation.
Proceedings of the Global Communications Conference, 2010

A differential binary message-passing LDPC decoder.
IEEE Trans. Commun., 2009

A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Convergence Speed and Throughput of Analog Decoders.
IEEE Trans. Commun., 2007

Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes.
IEEE Trans. Commun., 2006

A high-speed analog min-sum iterative decoder.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32, 8, 10) LDPC code.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Improving belief propagation on graphs with cycles.
IEEE Commun. Lett., 2004

On the dynamics of continuous-time analog iterative decoding.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

Comparison between continuous-time asynchronous and discrete-time synchronous iterative decoding.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Iterative decoding in analog CMOS.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003