Camille Leroux

Orcid: 0000-0002-7339-9142

According to our database1, Camille Leroux authored at least 49 papers between 2007 and 2023.

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Bibliography

2023
A DSEL for high throughput and low latency software-defined radio on multicore CPUs.
Concurr. Comput. Pract. Exp., 2023

A 8.34 nW Wake-Up Receiver Achieving -50dBm Sensitivity at 2.4GHz.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Low-Complexity Algorithm for the Minimum Distance Properties of PAC Codes.
Proceedings of the 12th International Symposium on Topics in Coding, 2023

AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Hellscape.
Proceedings of the SIGGRAPH Asia 2022 Computer Animation Festival, 2022

Ultra Low Power 32-bit Microcontroller With Minimal Instruction Set for Internet of Things Applications.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

2021
Tailored List Decoding of Polar Codes.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

A Flexible and Portable Real-time DVB-S2 Transceiver using Multicore and SIMD CPUs.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

2020
Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

2019
Fast and Flexible Software Polar List Decoders.
J. Signal Process. Syst., 2019

AFF3CT: A Fast Forward Error Correction Toolbox!
SoftwareX, 2019

Toward High-Performance Implementation of 5G SCMA Algorithms.
IEEE Access, 2019

2018
Low-Latency Software Polar Decoders.
J. Signal Process. Syst., 2018

High-performance software implementations of SCAN decoder for polar codes.
Ann. des Télécommunications, 2018

MIPP: a Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard.
Proceedings of the 4th Workshop on Programming Models for SIMD/Vector Processing, 2018

Transport Triggered Polar Decoders.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Custom Low Power Processor for Polar Decoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes.
J. Signal Process. Syst., 2017

Successive cancellation decoder for very long polar codes.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Improving performance of SCMA MPA decoders using estimation of conditional probabilities.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016
Lowering the Error Floor of Turbo Codes With CRC Verification.
IEEE Wirel. Commun. Lett., 2016

Lowering the error floor of double-binary turbo codes: The flip and check algorithm.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Beyond Gbps Turbo decoder on multi-core CPUs.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

A scalable 3-phase polar decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Memory reduction techniques for successive cancellation decoding of polar codes.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Energy consumption analysis of software polar decoders on low power processors.
Proceedings of the 24th European Signal Processing Conference, 2016

Hardware architecture for lowering the error floor of LTE turbo codes.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Multi-Gb/s Software Decoding of Polar Codes.
IEEE Trans. Signal Process., 2015

An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes.
Proceedings of the Languages and Compilers for Parallel Computing, 2015

Partial sums computation in polar codes decoding.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hardware implementation of a soft cancellation decoder for polar codes.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014
A Flexible NISC-Based LDPC Decoder.
IEEE Trans. Signal Process., 2014

High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing.
IEEE Trans. Signal Process., 2014

Software polar decoder on an embedded processor.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

2013
A Semi-Parallel Successive-Cancellation Decoder for Polar Codes.
IEEE Trans. Signal Process., 2013

Partial sums generation architecture for successive cancellation decoding of polar codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

2012
Hardware Implementation of Successive-Cancellation Decoders for Polar Codes.
J. Signal Process. Syst., 2012

Stochastic chase decoder for reed-solomon codes.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture.
J. Signal Process. Syst., 2011

Hardware architectures for successive cancellation decoding of polar codes.
Proceedings of the IEEE International Conference on Acoustics, 2011

2010
A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Stochastic Chase Decoding of Reed-Solomon Codes.
IEEE Commun. Lett., 2010

2009
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.
J. Signal Process. Syst., 2009

2008
Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design.
EURASIP J. Wirel. Commun. Netw., 2008

A highly parallel Turbo Product Code decoder without interleaving resource.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

On the higher efficiency of parallel Reed-Solomon turbo-decoding.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s.
Ann. des Télécommunications, 2007

Towards Gb/s turbo decoding of product code onto an FPGA device.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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