Sailesh Kottapalli

According to our database, Sailesh Kottapalli authored at least 8 papers between 2009 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Cascade Lake: Next Generation Intel Xeon Scalable Processor.

Mohamed Arafa, Bahaa Fahim, Sailesh Kottapalli, Akhilesh Kumar, Lily Pao Looi, Sreenivas Mandava, Andy Rudoff, Ian M. Steiner, Bob Valentine, Geetha Vedaraman, Sujal Vora

IEEE Micro, 2019

2015

Ivy Bridge Server: A Converged Design.

Irma Esmer Papazian, Sailesh Kottapalli, Jeff Baxter, Jeff Chamberlain, Geetha Vedaraman, Brian Morris

IEEE Micro, 2015

2014

Ivybridge server architecture: A converged server.

Irma Esmer Papazian, Sailesh Kottapalli

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2010

A 45 nm 8-Core Enterprise Xeon¯ Processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

IEEE J. Solid State Circuits, 2010

Westmere-EX: A 20 thread server CPU.

Dheemanth Nagaraj, Sailesh Kottapalli

Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2009

A 45nm 8-core enterprise Xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Nahalem-EX CPU architecture.

Sailesh Kottapalli, Jeff Baxter

Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

Power reduction techniques for an 8-core xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

Proceedings of the 35th European Solid-State Circuits Conference, 2009