Harry Muljono

According to our database, Harry Muljono authored at least 15 papers between 2001 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk Cancellation.

Harry Muljono, Kathy Peng, Linda Sun, Isaac Abraham, Charlie Lin, Yanjie Zhu, Chunrong Song

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

SkyLake-SP: A 14nm 28-Core xeon® processor.

Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT.

Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

IEEE J. Solid State Circuits, 2015

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010

A 45 nm 8-Core Enterprise Xeon¯ Processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

IEEE J. Solid State Circuits, 2010

2009

A 45nm 8-core enterprise Xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Power reduction techniques for an 8-core xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora

IEEE J. Solid State Circuits, 2007

2006

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.

Stefan Rusu, Harry Muljono, Brian S. Cherkauer

IEEE Micro, 2004

AC IO Loopback Design for High Speed µProcessor IO Test.

Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.

Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer

IEEE J. Solid State Circuits, 2003

A 400-MT/s 6.4-GB/s multiprocessor bus interface.

Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu

IEEE J. Solid State Circuits, 2003

2001

Itanium^TM Processor system bus design.

Alper Ilkbahar, Srinivas Venkataraman, Harry Muljono

IEEE J. Solid State Circuits, 2001