David Ayers

According to our database, David Ayers authored at least 10 papers between 2002 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

IEEE J. Solid State Circuits, 2015

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010

A 45 nm 8-Core Enterprise Xeon¯ Processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

IEEE J. Solid State Circuits, 2010

2009

A 45nm 8-core enterprise Xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Power reduction techniques for an 8-core xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora

IEEE J. Solid State Circuits, 2007

2006

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Power Grid Planning for Microprocessors and SOCS.

Qing K. Zhu, David Ayers

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003

Microarchitectural dI/dt Control.

Ed Grochowski, David Ayers, Vivek Tiwari

IEEE Des. Test Comput., 2003

2002

Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation.

Ed Grochowski, David Ayers, Vivek Tiwari

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002