Saion K. Roy

According to our database, Saion K. Roy authored at least 5 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation.

Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag

IEEE J. Solid State Circuits, March, 2025

2024

On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks.

Saion K. Roy, Naresh R. Shanbhag

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023

Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation.

Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures.

Saion K. Roy, Ameya Patil, Naresh R. Shanbhag

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Comprehending In-memory Computing Trends via Proper Benchmarking.

Naresh R. Shanbhag, Saion K. Roy

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022