Sandip Lashkare

Orcid: 0000-0003-2018-1681

According to our database1, Sandip Lashkare authored at least 14 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.
CoRR, 2023

Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron.
CoRR, 2023

Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing.
CoRR, 2023

FeFET-based MirrorBit cell for High-density NVM storage.
CoRR, 2023

2021
A Dual-Slope-Based Capacitance-to-Time Signal Conditioning Circuit for Leaky Capacitive Sensors.
IEEE Trans. Instrum. Meas., 2021

2020
India's Rise in Nanoelectronics Research.
CoRR, 2020

Temperature Dependence of Volatile Current shoot-up in PrMnO3 based Selector-less RRAM.
CoRR, 2020

Thermal Engineering of Volatile Switching in PrMnO3 RRAM: Non-Linearity in DC IV Characteristics and Transient Switching Speed.
Proceedings of the 2020 Device Research Conference, 2020

2019
Fundamental Limit on Network Size Scaling of Oscillatory Neural Networks due to PrMnO3 based Oscillator Phase Noise.
Proceedings of the Device Research Conference, 2019

2018
Stochastic learning in deep neural networks based on nanoscale PCMO device characteristics.
Neurocomputing, 2018

Transient Joule Heating in PrMnO3 RRAM enables ReLU type Neuron.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018

A case for multiple and parallel RRAMs as synaptic model for training SNNs.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

A Compact PrMnO3 Based Oscillator as an Alternative to CMOS Ring Oscillator in a Smart Temperature Sensor.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2016
A simple and efficient SNN and its performance & robustness evaluation method to enable hardware implementation.
CoRR, 2016


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