Stefan Dünkel

According to our database1, Stefan Dünkel authored at least 13 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2024
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR, 2024

2023
Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator.
Adv. Intell. Syst., June, 2023

Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.
CoRR, 2023

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.
CoRR, 2023

FeFET-based MirrorBit cell for High-density NVM storage.
CoRR, 2023

Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications.
Proceedings of the IEEE International Memory Workshop, 2023

2022
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.
CoRR, 2022

Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Experimental fabrication of an ESF3 floating gate flash cell in an FD-SOI process.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021
Hardware Functional Obfuscation With Ferroelectric Active Interconnects.
CoRR, 2021

Novel embedded single poly floating gate flash demonstrated in 22nm FDSOI technology.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical Preconditioning.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.
Proceedings of the 49th European Solid-State Device Research Conference, 2019


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