Sven Beyer

According to our database1, Sven Beyer authored at least 8 papers between 2003 and 2019.

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Bibliography

2019
Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical Preconditioning.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2010
Automated formal verification of processors based on architectural models.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009
Generating an Efficient Instruction Set Simulator from a Complete Property Suite.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

2006
Putting it all together - Formal verification of the VAMP.
Int. J. Softw. Tools Technol. Transf., 2006

2005
Putting it all together: formal verification of the VAMP.
PhD thesis, 2005

Towards the Formal Verification of Lower System Layers in Automotive Systems.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003
Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.
Proceedings of the Correct Hardware Design and Verification Methods, 2003


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