Veeresh Deshpande

According to our database1, Veeresh Deshpande authored at least 9 papers between 2011 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
3D Monolithic Integrated Indium Tin Oxide-Silicon Hybrid Leaky Integrate and Fire Neuron.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
Defect-Aware Physics-Based Compact Model for Ferroelectric nvCap: From TCAD Calibration to Circuit Co-Design.
CoRR, November, 2025

Symbol Detection in a MIMO Wireless Communication System Using a FeFET-coupled CMOS Ring Oscillator Array.
CoRR, November, 2025

Novel 4T-2C Ferroelectric Non-Volatile Memory Cell Featuring Non-Destructive Read.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024
Heracles: A HfO<sub>2</sub> Ferroelectric Capacitor Compact Model for Efficient Circuit Simulations.
CoRR, 2024

2023
Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.
CoRR, 2023

2022
A Ferroelectric Tunnel Junction-based Integrate-and-Fire Neuron.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2012
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices' Variability?
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011


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