Veeresh Deshpande

According to our database, Veeresh Deshpande authored at least 4 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.

Paritosh Meihar, Rowtu Srinu, Sandip Lashkare, Ajay Kumar Singh, Halid Mulaosmanovic, Veeresh Deshpande, Stefan Dünkel, Sven Beyer, Udayan Ganguly

CoRR, 2023

2022

A Ferroelectric Tunnel Junction-based Integrate-and-Fire Neuron.

Paolo Gibertini, Luca Fehlings, Suzanne Lancaster, Quang T. Duong, Thomas Mikolajick, Catherine Dubourdieu, Stefan Slesazeck, Erika Covi, Veeresh Deshpande

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2012

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.

Veeresh Deshpande, Sylvain Barraud, Xavier Jehl, Romain Wacquez, Maud Vinet, Remi Coquand, B. Roche, B. Voisin, François Triozon, C. Vizioz, L. Tosti, Bernard Previtali, P. Perreau, T. Poiroux, Marc Sanquer, Olivier Faynot

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011

Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices' Variability?

Xavier Jehl, B. Roche, Marc Sanquer, B. Voisin, Romain Wacquez, Veeresh Deshpande, Bernard Previtali, Maud Vinet, J. Verduijn, Giuseppe Carlo Tettamanzi, Sven Rogge, D. Kotekar-Patil, Matthias Ruoff, D. Kern, D. A. Wharam, M. Belli, Enrico Prati, Marco Fanciulli

Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011